Method and system for executing new instructions

ABSTRACT

A method for converting instructions is provided. The method is used in a processor and includes: receiving an instruction; generating an unknown instruction exception when the received instruction is an unknown instruction; in response to the unknown instruction exception, entering a system management mode; and in the system management mode, executing the following steps through a conversion program: determining whether the received instruction is a new instruction; and simulating the execution of the received instruction by executing at least one old instruction when the received instruction is a new instruction.

CROSS REFERENCE TO RELATED APPLICATIONS

This Application claims priority of China Patent Application No.202011591545.6, filed on Dec. 29, 2020, China Patent Application No.202011591546.0, filed on Dec. 29, 2020, the entirety of which isincorporated by reference herein.

BACKGROUND Technical Field

The present disclosure generally relates to the field ofmicroelectronics. More specifically, aspects of the present disclosurerelate to a method and system for executing new instructions.

Description of the Related Art

Processor technology has developed rapidly over the years. With theenhancement of processor functions, subsequent-generation processorswill often add new instructions on the basis of previous-generationprocessors. Since the previous-generation processors cannot execute thenew instructions supported by the subsequent-generation processors, anunknown instruction exception (#UD) will be generated when theprevious-generation processors execute the new instructions, wherein theunknown instruction exception may cause the process containing the newinstructions to be terminated by the operating system, and cause theapplication or operating system containing the new instructions to beunable to execute on the previous-generation processors.

Therefore, there is a need for a method and system for executing newinstructions to achieve the purpose of executing new instructions onprevious-generation processors.

SUMMARY

The following summary is illustrative only and is not intended to belimiting in any way. That is, the following summary is provided tointroduce concepts, highlights, benefits and advantages of the novel andnon-obvious techniques described herein. Select, not all,implementations are described further in the detailed description below.Thus, the following summary is not intended to identify essentialfeatures of the claimed subject matter, nor is it intended for use indetermining the scope of the claimed subject matter.

Therefore, the main purpose of the present disclosure is to provide amethod and system for converting instructions, so as to achieve thepurpose of executing new instructions without changing the hardwarearchitecture of the previous-generation processing core.

In an exemplary embodiment, a method for executing new instructions,comprising: receiving an instruction; generating an unknown instructionexception when the received instruction is an unknown instruction; inresponse to the unknown instruction exception, entering a systemmanagement mode; and in the system management mode, executing thefollowing steps through a conversion program: determining whether thereceived instruction is a new instruction; and simulating the executionof the received instruction by executing at least one old instructionwhen the received instruction is a new instruction.

In an exemplary embodiment, a system for executing new instructions,comprising: an instruction decoding unit, receiving an instruction, anddetermining whether the received instruction is an unknown instruction;an instruction submission unit, generating an unknown instructionexception when the received instruction is an unknown instruction; inresponse to the unknown instruction exception, the system for executingthe new instruction executes the following steps through a conversionprogram: determine whether the received instruction is a newinstruction; and simulating the execution of the received instruction byexecuting at least one old instruction when the received instruction isa new instruction.

Through the method and the system for executing new instructionsprovided in the present disclosure, new instructions can be executed onthe previous-generation processors without modifying the hardwarearchitecture of the processing cores.

BRIEF DESCRIPTION OF DRAWINGS

The accompanying drawings are included to provide a better understandingof the disclosure, and are incorporated in and constitute a part of thepresent disclosure. The drawings illustrate implementations of thedisclosure and, together with the description, serve to explain theprinciples of the disclosure. It should be appreciated that the drawingsare not necessarily to scale as some components may be shown out ofproportion to their size in actual implementation in order to clearlyillustrate the concept of the present disclosure.

FIG. 1 shows a schematic diagram of a system for executing newinstructions in accordance with one embodiment of the presentdisclosure.

FIG. 2 is a block diagram of the processor in accordance with oneembodiment of the present disclosure.

FIG. 3 is a flowchart showing the execution of the new instructionaccording to the first embodiment of the present disclosure.

FIG. 4 shows a flowchart of processing the received instructionaccording to the first embodiment of the present disclosure.

FIG. 5 shows a flowchart of entering the system management modeaccording to the first embodiment of the present disclosure.

FIG. 6 is a flowchart showing the processing of the simulator accordingto the first embodiment of the present disclosure.

FIG. 7 shows a processing flowchart of the conversion program accordingto the first embodiment of the present disclosure.

FIG. 8 shows an example of processing unknown instructions in the systemmanagement mode according to the first embodiment of the presentdisclosure.

FIGS. 9A˜9B show a flowchart of exiting the system management modeaccording to the first embodiment of the present disclosure.

FIG. 10 is a schematic diagram of a system for executing newinstructions according to the second embodiment of the presentdisclosure.

FIG. 11 is a structural diagram of the processor according to the secondembodiment of the present disclosure.

FIG. 12 is a flowchart showing the execution of the new instructionaccording to the second embodiment of the present disclosure.

FIG. 13 is a flowchart showing the processing of the receivedinstruction according to the second embodiment of the presentdisclosure.

FIG. 14 is a flow chart of processing the received instruction in amicrocode handler for handling unknown instruction exceptions accordingto the second embodiment of the present disclosure.

FIGS. 15A to 15B are schematic diagrams showing the system for executingnew instructions according to the third embodiment of the presentdisclosure.

FIG. 16 is a flowchart of processing a received instruction according toanother embodiment of the present disclosure.

FIG. 17 is a schematic diagram of a system for executing newinstructions according to the fourth embodiment of the presentdisclosure.

FIG. 18 shows a flowchart of executing a new instruction according to anembodiment of the present disclosure.

FIG. 19 is a flow chart of executing a new instruction according to anembodiment of the present disclosure.

FIG. 20 is a flowchart showing the conversion of the new instructionaccording to an embodiment of the present disclosure.

FIG. 21 illustrates an exemplary operating environment for implementingembodiments of the present disclosure.

DETAILED DESCRIPTION

Various aspects of the disclosure are described more fully below withreference to the accompanying drawings. This disclosure may, however, beembodied in many different forms and should not be construed as limitedto any specific structure or function presented throughout thisdisclosure. Rather, these aspects are provided so that this disclosurewill be thorough and complete, and will fully convey the scope of thedisclosure to those skilled in the art. Based on the teachings hereinone skilled in the art should appreciate that the scope of thedisclosure is intended to cover any aspect of the disclosure disclosedherein, whether implemented independently of or combined with any otheraspect of the disclosure. For example, an apparatus may be implementedor a method may be practiced using number of the aspects set forthherein. In addition, the scope of the disclosure is intended to coversuch an apparatus or method which is practiced using another structure,functionality, or structure and functionality in addition to or otherthan the various aspects of the disclosure set forth herein. It shouldbe understood that any aspect of the disclosure disclosed herein may beembodied by one or more elements of a claim.

The word “exemplary” is used herein to mean “serving as an example,instance, or illustration.” Any aspect described herein as “exemplary”is not necessarily to be construed as preferred or advantageous overother aspects. Furthermore, like numerals refer to like elementsthroughout the several views, and the articles “a” and “the” includesplural references, unless otherwise specified in the description.

It should be understood that when an element is referred to as being“connected” or “coupled” to another element, it may be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. Other words used to describe therelationship between elements should be interpreted in a like fashion.(e.g., “between” versus “directly between”, “adjacent” versus “directlyadjacent”, etc.).

In order to better describe the embodiments of the present disclosure,the specific terms used in the present disclosure are firstly defined asbelow.

Old instructions: the instructions natively supported byprevious-generation processors are called native instructions, alsoknown as existing instructions or old instructions.

Unknown instructions: instructions not natively supported byprevious-generation processors.

New instruction: compared with a previous-generation processor, theinstruction newly supported by the subsequent-generation processor. Thenew instruction cannot be recognized by the previous-generationprocessor, so it is an unknown instruction to the previous-generationprocessor.

New architecture registers: compared with the previous-generationprocessors, the new architecture registers supported by thesubsequent-generation processors. The new architecture register does notexist in the previous- generation processor. Therefore, when the newinstruction using the new architecture register is simulated andexecuted on the previous-generation processor, the new architectureregister needs to be simulated.

Unrecognized instructions: among unknown instructions, the remainingpart of the instructions after the new instructions is removed. That is,unrecognized instructions refer to instructions that are not nativelysupported by subsequent-generation processors.

Model specific register: a type of register in the processor that can beused to perform some specific functions.

Traps: traps are generally caused by soft interrupt instructions (suchas INT instruction). When an instruction causes a trap exception, itdoes not mean that there is an error in the execution of the instructionitself. Therefore, when an instruction causes a trap exception, theprocessor will continue to execute the next instruction of thisinstruction. For example, when a software developer debugs the softwarecode, he/she can set breakpoints in the code. When program code with abreakpoint is executed on the processor, and when the execution reachesthe breakpoint, a trap will be generated, so that the execution of theprogram code will be suspended at the breakpoint. Software developerscan view the value of each architecture register in the processor or thevalue of each variable in the program code through the microcode handlerthat handles the trap when the program code is executed to a breakpoint.According to the value of each structure register or the value of eachvariable in the program code, it is determined whether the program codeis executed normally when the execution reaches the breakpoint.

In addition, in this specification, the simulation and the emulationhave the same meanings, and the simulator and the emulator have the samemeanings, and simulate and emulate have the same meanings.

The processor of the present disclosure can be a processor with reducedinstruction set computing (RISC) (such as ARM/MIPS/RISC-V instructionset), complex instruction set computing (CISC) (such as x86 instructionset), or processors of other types of instruction set, or a processorthat can support multiple different instruction set architectures at thesame time (for example, a processor that support both x86 instructionset and ARM instruction set). The type of instruction set supported bythe processor is not particularly limited in the present disclosure, butfor the convenience of description, a processor supporting the X86instruction set is used to describe the embodiments of the presentdisclosure. In addition, as is well known to those skilled in the art,the x86 processor interprets macroinstructions into at least onemicroinstruction or sequence of microinstructions according to thesequence of the original program. However, the execution ofmicroinstructions is performed in an out-of-order manner to improveexecution efficiency, but the retire process after the microinstructionsare executed is still performed according to the sequence of theoriginal program.

There are a variety of embodiments in the present disclosure. Thefollowing four examples are used to describe the four main embodimentsof the present disclosure. The first embodiment describes theimplementation of simulating the execution of new instructions in thesystem management mode. The second embodiment describes theimplementation of simulating the execution of the new instruction in thesame execution mode as the new instruction. The third embodiment and thefourth embodiment describe the implementation of simulating theexecution of the new instruction through the operating system, wherein adedicated processing core is used to complete the conversion operationof the new instruction in the fourth embodiment. The first embodimentwill be described first.

[First Embodiment]

FIG. 1 shows a schematic diagram of a system 100 for executing newinstructions in accordance with one embodiment of the presentdisclosure. As shown in FIG. 1, the system 100 for executing newinstructions includes a processor 110, an operating system 120, anapplication program 130, and a simulator 142. The operating system 120runs on the processor 110 and is used to manage the processor 110. Theapplication program 130 runs on the operating system 120, and can usevarious functions provided by the processor 110 and other hardware (notshown, such as a hard disk, a network card, etc.) through the operatingsystem 120. The simulator 142 runs on the processor 110 in a systemmanagement mode (SMM). The operating system 120 or the applicationprogram 130 cannot perceive the execution process of the simulator 142.That is, all operations performed by the simulator 142 are transparentto the operating system 120 or the application 130.

When the processor 110 executes an unknown instruction of theapplication 130 or the operating system 120, the processor 110 entersthe system management mode and sends the unknown instruction to thesimulator 142 for processing. When the unknown instruction is a newinstruction, the simulator 142 will simulate and execute the newinstruction. It should be noted that the source code of the application130 or the operating system 120 is generally written in a high-levellanguage (such as C language, C++ language, etc.) and/or a low-levellanguage (such as assembly language, etc.). After the source code iscompiled with a compiler, executable code that can be executed by theprocessor is generated. Executable code consists of instructions thatcan be directly executed by the processor. In the present disclosure,the application program 130 or the operating system 120 refers to theexecutable code generated after the source code of the applicationprogram 130 or the operating system 120 is compiled by a compiler. Inthe following, the processing of the unknown instruction 132 by theprocessor 110 in FIG. 1 may be taken as an example to briefly describethe processing procedure of the system 100 for executing the newinstructions.

As shown in FIG. 1, the processor 110 comprises an interruptpreprocessing unit 112 and a system management mode exit/entry 114. Thesystem management mode exit/entry 114 comprises a system management modeentry 1142 and a system management mode exit 1144. In FIG. 1, the solidarrow with a digital number indicates the transmission direction ofinstruction information, and the dashed arrow with a digital numberindicates the transmission direction of the instruction simulationexecution result. The entire process of the processor 110 processing theunknown instruction 132 is described below.

First, the processor 110 receives an instruction 118 in the application130 to complete a specified function (as shown by the solid arrow 1).After receiving the instruction 118, the processor 110 determineswhether the instruction 118 is an unknown instruction 132. When theinstruction 118 is an unknown instruction 132, the processor 110generates an unknown instruction exception (#UD). In response to theunknown instruction exception, the interrupt preprocessing unit 112executes a microcode processing procedure for the unknown instructionexception. In the microcode processing procedure for the unknowninstruction exception, the interrupt preprocessing unit 112 sets aemulation flag and generates a system management interrupt (#SMI), andat the same time sends the instruction information of the unknowninstruction 132 to the system management mode exit/entry 114 (as shownby the solid arrow 2). How to generate unknown instruction exceptionsand system management interrupts is the common knowledge of thoseskilled in the art, so the details will be omitted. In an embodiment,the processor 110 is a processor supporting the x86 instruction set, andthe interrupt preprocessing unit 112 is a microcode control unit. Inactual operation, those skilled in the art can modify the microcodeprocessing procedure of the unknown instruction exception stored in theinterrupt preprocessing unit 112 to add the function of setting theemulation flag, obtaining the instruction information of the unknowninstruction, and generating the system management interrupt. Since thesemicrocodes are different depending on the processor version, thoseskilled in the art may write corresponding microcodes according toactual conditions.

Then, the processor 110 enters the system management mode by executingthe system management mode entry 1142, and sends the instructioninformation of the unknown instruction 132 to the simulator 142 (asshown by the solid arrow 3). In the system management mode, thesimulator 142 determines whether the unknown instruction 132 is a newinstruction. When the unknown instruction 132 is a new instruction, thesimulator 142 simulates the execution of the new instruction. Aftersimulating the execution of the new instruction, the simulator 142 sendsthe simulation execution result to the system management mode exit/entry114 (as shown by the dashed arrow 4). Then, the processor 110 sends thesimulation execution result to the application program 130 through thesystem management mode exit 1144 (as shown by the dotted arrow 5), andexits the system management mode. Therefore, the processor 110 hasprocessed the unknown instruction 132. In one embodiment, the simulator142 may store the intermediate calculation results generated during thesimulation execution into the system management memory (SMRAM) duringthe process of simulating the execution of the new instruction.

FIG. 2 is a block diagram of the processor in accordance with oneembodiment of the present disclosure. As shown in FIG. 2, the processor200 on the left of the dotted line is a structural diagram of theprocessor 110 shown in FIG. 1, and the simulator 142 and the conversionprogram 145 on the right of the dotted line run on the processor 200 inthe system management mode. In an embodiment, the functions performed bythe conversion program 145 are implemented in a conversion module, orthe conversion program 145 can also be regarded as a conversion modulein the system 100 that executes the new instructions.

As shown in FIG. 2, the processor 200 comprises an instructiontranslation lookaside buffer (ITLB) 201, an instruction cache 202, and abranch predictor 203. When the processor 200 executes an instruction inthe application 130 or the operating system 120, the instructiontranslation lookaside buffer 201 of the processor 200 receives theaddress of the instruction. The branch predictor 203 is used to predictthe conditional branch and transmit the branch prediction result to theinstruction cache 202. The instruction cache 202 obtains the address ofthe received instruction from the instruction translation lookasidebuffer 201 according to the branch prediction result, and then theprocessor 200 performs further processing on the received instruction.

As shown in FIG. 2, the processor 200 further comprises an instructiondecoding unit 230. The instruction decoding unit 230 determines whetherthe received instruction is an unknown instruction, and then generatesat least one microinstruction, wherein the microinstruction comprises anunknown instruction identifier, which is used to indicate whether thereceived instruction is an unknown instruction. When the unknowninstruction identifier is the first value, it means that the receivedinstruction is an unknown instruction. When the unknown instructionidentifier is the second value, it means that the received instructionis an old instruction. In one embodiment, the first value is 1, and thesecond value is 0.

The processor 200 also comprises a renaming unit 204, a reservationstation 205, an execution unit 206, a memory access unit 207, and areordering buffer 240, the interrupt preprocessing unit 112, and thearchitecture register 260. After the renaming unit 204 receives themicroinstruction from the instruction decoding unit 230, the renamingunit 204 renames the received microinstruction, wherein themicroinstruction comprises an unknown instruction identifier (UD). Then,the renaming unit 204 sends the renamed microinstruction to thereservation station 205 and the reordering buffer 240. The reservationstation 205 sends the microinstruction to the execution unit 206 or thememory access unit 207 for further processing according to the type ofthe microinstruction. After the reordering buffer 240 receives themicroinstruction, the reordering buffer 240 stores the microinstructionin an instruction entry. The reordering buffer 240 comprises multipleinstruction entries, and each instruction entry comprises an unknowninstruction identifier field, which is used to store the unknowninstruction identifier in the microinstruction.

The reordering buffer 240 comprises an instruction retiring unit 245.When the microinstruction satisfies the retire condition, theinstruction retiring unit 245 retires the microinstruction. In theprocess of retiring the microinstruction, when the microinstruction isexecuted without exception, the instruction retiring unit 245 updatesthe architecture register 260 according to the execution result of themicroinstruction. When an exception occurs during the execution of themicroinstruction, the instruction retiring unit 245 reports theexception. In response to the exception, the processor 200 executes themicrocode handler of the exception.

In the process of retiring the microinstruction, the instructionretiring unit 245 generates an unknown instruction exception (#UD) whenthe unknown instruction identifier of the microinstruction is the firstvalue. In response to the unknown instruction exception, the processor200 executes a microcode handler of the unknown instruction exception.In the microcode handler of the unknown instruction exception, theprocessor 200 stores an emulation flag whose value is the first value inthe microarchitecture register 220 and generates a system managementinterrupt (#SMI). In response to the system management interrupt, theprocessor 200 may enter the system management mode through the systemmanagement mode entry 1142 shown in FIG. 1 according to the emulationflag stored in the microarchitecture register 220. In the systemmanagement mode, the processor 200 processes the received instructionthrough the simulator 142. First, the simulator 142 determines whetherthe received instruction is a new instruction. When the receivedinstruction is a new instruction, the simulator 142 may simulate theexecution of the received instruction. In the process of simulating theexecution of the received instruction, the simulator 142 may store theintermediate calculation result in the system management memory (SMRAM).It should be noted that when the emulation flag is the first value, itmeans that the simulator 142 is required to process the receivedinstruction. When the emulation flag is the second value, it means thatthe simulator 142 is not required to process the received instruction.

After the simulator 142 processes the received instruction, theprocessor 200 exits the system management mode by executing the systemmanagement mode exit 1144 as shown in FIG. 1. The system management modeexit 1144 sets the emulation flag stored in the microarchitectureregister 220 to the second value, and then exits the system managementmode. When the processor 200 executes another received instruction, andthe another received instruction is an unknown instruction, theprocessor 200 may set the emulation flag stored in the microarchitectureregister 220 to the first value during the processor 200 executes themicrocode handler of the unknown instruction exception. Then, theprocessor 200 processes the another received instruction according tothe processing procedure as described above.

FIG. 3 is a flowchart showing the execution of the new instructionaccording to the first embodiment of the present disclosure. Pleaserefer to both FIGS. 2 and 3. As shown in FIG. 3, the instructiondecoding unit 230 receives an instruction (S305). When the receivedinstruction is an unknown instruction, the instruction retiring unit 245generates an unknown instruction exception (S310). In response to theunknown instruction exception, the processor 200 enters a systemmanagement mode (S315), and determines whether the received instructionis a new instruction through a conversion program (S320). When thereceived instruction is a new instruction, the processor 200 simulatesthe execution of the received instruction by executing at least one oldinstruction (S325). The detailed description is as follows: theinstruction decoding unit 230 first executes step S305.

In step S305, the instruction decoding unit 230 receives an instruction.Specifically, the instruction decoding unit 230 receives the instructionfrom the instruction cache 202. Then, the processor 200 executes stepS310.

In step S310, when the received instruction is an unknown instruction,the instruction retiring unit 245 generates an unknown instructionexception. Specifically, as described above, after the instructiondecoding unit 230 determines that the received instruction is an unknowninstruction, the instruction decoding unit 230 generates amicroinstruction, wherein the microinstruction comprises an unknowninstruction identifier whose value is a first value. Then, theinstruction decoding unit 230 sends the microinstruction to the renamingunit 204. The renaming unit 204 performs renaming processing on themicroinstruction, and then sends the microinstruction to the reorderingbuffer 240. The reordering buffer 240 stores the microinstruction in aninstruction entry. When the microinstruction satisfies the retirecondition, the instruction retiring unit 245 reads the microinstructionfrom the instruction entry, and retires the microinstruction. Since theunknown instruction identifier of the microinstruction is the firstvalue, the instruction retiring unit 245 generates an unknowninstruction exception. Then, the processor 200 executes step S315.

In step S315, in response to the unknown instruction exception, theprocessor 200 enters a system management mode (SMM). Specifically, inresponse to the unknown instruction exception, the processor 200executes a microcode handler of the unknown instruction exception. Inthe microcode handler of the unknown instruction exception, theprocessor 200 writes an emulation flag (EF) whose value is the firstvalue into the microarchitecture register 220, and generates a systemmanagement interrupt (#SMI). In response to the system managementinterrupt, the processor 200 enters the system management mode accordingto the emulation flag through the system management mode entry 1142shown in FIG. 1. Then, step S320 is executed.

In step S320, in the system management mode, the processor 200determines whether the received instruction is a new instruction througha conversion program. As for how the conversion program determineswhether the received instruction is a new instruction, the followingwill describe in detail with reference to FIG. 7. In one embodiment, theconversion program may be pre-stored in a basic input output system(BIOS). Those skilled in the art know that the basic input output systemmay be executed when the system 100 for executing new instructions isstarted up. The basic input output system comprises the codes forinitializing the system management mode. When the system 100 forexecuting new instructions executes the codes for initializing thesystem management mode, the conversion program is loaded into the systemmanagement memory (SMRAM). Then, the processor 200 may directly executethe conversion program stored in the system management memory afterentering the system management mode. Then, the processor 200 executesstep S325.

In step S325, when the received instruction is a new instruction, theprocessor 200 simulates the execution of the received instruction byexecuting at least one old instruction. Specifically, when the receivedinstruction is a new instruction, the processor 200 first converts thereceived instruction into at least one old instruction through theconversion program. Then, the processor 200 executes the at least oneold instruction. For a more detailed description, refer to thedescription of steps S615, S620, S625, and S630 in FIG. 6 below.

In an embodiment, the received instruction is an instruction setarchitecture instruction, and the at least one old instruction is aninstruction set architecture instruction. In another embodiment, thereceived instruction is an x86 instruction, an ARM instruction, a RISC-Vinstruction, or a MIPS instruction, and the at least one old instructionis an x86 instruction, an ARM instruction, a RISC-V instruction, or aMIPS instruction.

FIG. 4 shows a flowchart of processing the received instructionaccording to the first embodiment of the present disclosure. Pleaserefer to both FIG. 2 and FIG. 4. As shown in FIG. 4, the instructiondecoding unit 230 receives an instruction (S405), and determines whetherthe received instruction is an unknown instruction (S410). When thereceived instruction is an unknown instruction, the processor enters thesystem management mode to process the received instruction. Since stepS405 is the same as step S305 in FIG. 3, the details of step S405 willbe omitted. Step S410 is described below.

In step S410, the instruction decoding unit 230 determines whether thereceived instruction is an unknown instruction. Specifically, theinstruction decoding unit 230 decodes the received instruction to obtaindecoding information of the received instruction. In one embodiment, thedecoding information comprises a prefix, an escape code, an operationcode (opcode), an operand mode (ModR/M), other decoding information, andso on. Then, the instruction decoding unit 230 determines whether thereceived instruction is an unknown instruction according to the decodinginformation. For example, the operation codes of the old instructionsnatively supported by the processor 110 may be stored in a lookup table.The instruction decoding unit 230 may check whether the operation codeof the received instruction is stored in the lookup table. When theoperation code of the received instruction is stored in the lookuptable, it means that the received instruction is an old instruction;otherwise, it means that the received instruction is an unknowninstruction. In an embodiment, the lookup table is stored in theinstruction decoding unit 230.

When the received instruction is an old instruction (“No” in step S410),step S435 is executed. In step S435, the processor 200 normallyprocesses the received instruction. As for how to process the receivedinstruction normally, such as converting the old instruction into thecorresponding microinstruction, and executing the correspondingmicroinstruction, it is the common knowledge of those skilled in the artand so the details will be omitted. When the received instruction is anunknown instruction (“Yes” in step S410), step S415 is executed.

In step S415, the processor 200 writes an emulation flag (EF) into amicroarchitecture register 220. Specifically, when the receivedinstruction is an unknown instruction, the instruction decoding unit 230generates a microinstruction, and the unknown instruction identifier ofthe microinstruction is the first value. In one embodiment, themicroinstruction is a no operation microinstruction (NOP). Theinstruction decoding unit 230 sends the microinstruction to the renamingunit 204. The renaming unit 204 renames the microinstruction. Then, therenaming unit 204 sends the microinstruction to the reordering buffer240. The reordering buffer 240 stores the microinstruction in its owninstruction entries. When the microinstruction is retired, theinstruction retiring unit 245 generates an unknown instruction exceptionsince the unknown instruction identifier of the microinstruction is thefirst value. In response to the unknown instruction exception, theprocessor 200 executes a microcode handler of the unknown instructionexception. In the microcode handler of the unknown instructionexceptions, the processor 200 writes an emulation flag into themicroarchitecture register 220. In addition, the processor 200 alsostores the information of the received instruction and the operatingenvironment information of the received instruction in themicroarchitecture register 220. Then, in the microcode handler of theunknown instruction exception, the processor 200 generates a systemmanagement interrupt (#SMI). In an embodiment, the information of thereceived instruction comprises an instruction pointer of the receivedinstruction. In another embodiment, the information of the receivedinstruction comprises the instruction pointer of the receivedinstruction and the machine code of the received instruction. Theoperating environment information comprises the operating modes of thereceived instruction (that is, the operating modes of the processor 200when the processor 200 executes the received instruction). For example,the operating modes comprise a real mode, a protected mode, a v8086mode, a compatibility mode, and a long mode, and so on. Then, theprocessor 200 executes step S420.

In step S420, the processor 200 enters a system management mode.Specifically, in response to the system management interrupt, theprocessor 200 enters the system management mode by executing the systemmanagement mode entry 1142 shown in FIG. 1. As for the details of theprocessor 200 entering the system management mode, it will be describedin detail later with reference to FIG. 5. Then, the processor 200executes step S425.

In step S425, the processor 200 processes the received instruction. Asfor how the processor 200 processes the received instruction, thefollowing will describe in detail with reference to FIGS. 6-8. Then, theprocessor 200 executes step S430.

In step S430, the processor 200 exits the system management mode, andthe flow ends. Specifically, the processor 200 exits the systemmanagement mode by executing the system management mode exit 1144 shownin FIG. 1. As for how the processor 200 exits the system managementmode, the following will describe in detail with reference to FIGS.9A˜9B.

FIG. 5 shows a flowchart of entering the system management modeaccording to the first embodiment of the present disclosure. FIG. 5 is aprocessing flow of the microcode handler corresponding to the systemmanagement mode entry 1142 shown in FIG. 1. Please refer to FIG. 2 andFIG. 5. As shown in FIG. 5, the processor 200 disables the interrupt(S505), and determines whether the emulation flag is the first value(S510). When the determination result of step S510 is “Yes”, theprocessor 200 enters the system management mode. The detaileddescription is as follows: the processor 200 first executes step S505.

In step S505, the processor 200 disables interrupts. Those skilled inthe art know that interrupts are disabled in the system management mode.Therefore, the present disclosure also continues this architecturalrequirement to disable interrupts. As for how to disable interrupts, forexample, the processor 200 clears the IF flag to disable maskableinterrupts, clears the TF flag to disable single-step interrupts, andclears DR7 to disable breakpoint interrupts. Then, the processor 200executes step S510.

Next, in step S510, the processor 200 determines whether the emulationflag is the first value. Specifically, the processor 200 determineswhether the emulation flag stored in the microarchitecture register 220is the first value. When the determination result is “No”, step S530 isexecuted to execute the normal processing flow of entering the systemmanagement mode. Those skilled in the art know the normal processingflow of the system management mode, so the details related to the normalprocessing flow will be omitted. When the determination result is “Yes”,the processor 200 executes step S515.

In step S515, the processor 200 generates an entering system managementmode notification (Assert #smmact) to notify the chipset that theprocessor 200 has entered the system management mode. As for how togenerate the notification of entering the system management mode, it isthe common knowledge of those skilled in the art, so the details will beomitted. Then, the processor 200 executes step S520.

In step S520, the processor 200 stores the emulation flag, theinformation of the received instruction, and the operating environmentinformation into the system management memory. Specifically, theprocessor 200 reads the emulation flag, the information of the receivedinstruction, and the operating environment information from themicroarchitecture register 220, and stores the read emulation flag, theinformation of the received instruction, and the operating environmentinformation in the system management memory. At the same time, thecontent in the architecture register 260 (that is, the current state ofthe processor 200) may also be stored in the system management memory.The information stored in the system management memory is shown in TABLE1 below.

TABLE 1 Information of the Operating Architectural Emulation receivedenvironment register flag instruction information . . . . . . . . . . .. . . . . . .

Then, the processor 200 executes step S525. The processor 200establishes a system management mode execution environment, and entersthe system management mode. How to establish the execution environmentof the system management mode and how to enter the system managementmode is the common knowledge of those skilled in the art, so the detailswill be omitted.

It should be noted that, in the actual operation of entering the systemmanagement mode through the system management mode entry 1142 in FIG. 1shown in FIG. 5, after the system management interrupt (#SMI) isgenerated, those skilled in the art may add some microcodes used toexecute and save the emulation flag, the information of the receivedinstructions and the operating environment information to the systemmanagement memory (SMRAM) in the microcodes corresponding to enteringthe system management mode, and ensure that these data/information maynot be overwritten when the processor 200 switches to the systemmanagement mode. Furthermore, due to the prior art, the processor 200 inthe system management mode may access the system management memory(SMRAM), so those skilled in the art may make modifications based onthis part of the microcodes to achieve the purpose of the processor toaccess the data/information. Since these microcodes may vary dependingon the processor version, those skilled in the art may writecorresponding microcodes according to actual conditions.

Then, the processor 200 processes the received instruction in the systemmanagement mode (as shown in step S425 in FIG. 4). The followingdescribes how the processor 200 processes the received instructions inthe system management mode with reference to FIGS. 6˜8.

FIG. 6 is a flowchart showing the processing of the simulator accordingto the first embodiment of the present disclosure. As mentioned above,the processor 200 uses the simulator 142 to process the receivedinstruction in the system management mode. Please refer to FIGS. 2 and6. As shown in FIG. 6, in the system management mode, the simulator 142establishes a simulation operating environment (S605), and thendetermines whether the emulation flag is the first value (S610). Whenthe determination result of step S610 is “Yes”, the simulator 142converts the received instruction through the conversion program, andgenerates a conversion result (S615). Then, the simulator 142 processesthe conversion result. The detailed description is as follows. First,the simulator 142 executes step S605.

In step S605, the simulator 142 establishes a simulation operatingenvironment. Specifically, the simulator 142 reads the emulation flag,the information of the received instruction, the operating environmentinformation of the received instruction, and the information of thearchitecture register from the system management memory. In thesubsequent steps, the simulator 142 may use the read information tosimulate the execution of the received instructions. Then, the simulator142 executes step S610.

In step S610, the simulator 142 determines whether the emulation flag isthe first value. Specifically, the simulator 142 determines whether theemulation flag read in step S605 is the first value. When thedetermination result is “No”, the simulator 142 executes step S645. Instep S645, the simulator 142 executes the normal processing flow of thesystem management mode. The normal processing flow of the systemmanagement mode is the common knowledge of those skilled in the art, sothe details related to the normal processing flow will be omitted. Whenthe determination result of step S610 is “Yes”, the simulator 142executes step S615.

In step S615, the simulator 142 converts the received instructionthrough the conversion program 145, and generates a conversion result.The structure of the conversion result is shown in TABLE 2 below,wherein the conversion result comprises two fields: a result field and acontent field. When the result field is the first value, it means thatthe conversion is successful, and the content field comprises at leastone old instruction converted from the received instruction and thelength of the received instruction. When the result field is the secondvalue, it means that the conversion failed, and the content fieldcomprises an exception code. As for how to use the conversion program145 to convert the received instruction, it will be described in detaillater with reference to FIG. 7.

TABLE 2 Result Content . . . . . .

In step S620, the simulator 142 determines whether the conversionprogram successfully converts the received instruction. Specifically,the simulator 142 determines whether the conversion program successfullyconverts the received instruction according to the result field in theconversion result. When the result field of the conversion result is thefirst value, the determination result is “Yes” and the simulator 142executes step S625. When the result field of the conversion result isthe second value, the determination result is “No”, the simulator 142generates a simulation execution result according to the conversionresult, and then executes step S630. The structure of the simulationexecution result is shown in TABLE 3 below, which comprises two fields:a result field and a detail field. When the result field of thesimulation execution result is the first value, it means that thesimulation execution is successful, and the operation result obtainedafter the simulation execution is stored in the detail field. When theresult field of the simulation execution result is the second value, itmeans that the simulation execution failed and the exception code isstored in the detail field. When the result field of the conversionresult is the second value, the simulation execution result generatedaccording to the conversion result is shown in TABLE 3-1 below. Theexception code in the detail field in TABLE 3-1 is the exception code inthe content field of the conversion result.

TABLE 3 Result Detail . . . . . .

TABLE 3-1 Result Detail Second Exception value code

Furthermore, when the determination result of step S620 is that theconversion program successfully converts the received instruction (thatis, the determination result of step S620 is “Yes”), the simulator 142executes step S625. In step S625, the simulator 142 obtains at least oneold instruction from the conversion result, and executes the at leastone old instruction. Specifically, the simulator 142 obtains the atleast one old instruction and the length of the received instructionfrom the content field of the conversion result. Then, the simulator 142instructs the processor 200 to execute the at least one old instructionthrough a call instruction or a jump instruction. The processor 200decodes the at least one old instruction into at least onemicroinstruction, executes the at least one microinstruction, andgenerates a simulation execution result. When a runtime exception occursduring the execution of the at least one microinstruction by theprocessor 200, the content field of the simulation execution result isshown in the following TABLE 3-2. The result field of the simulationexecution result in TABLE 3-2 is the second value, indicating that thesimulation execution failed. The detail field of the simulationexecution result is the exception code, indicating that the number ofthe runtime exception. When the processor 200 successfully executes theat least one microinstruction, the content field of the simulationexecution result is shown in the following TABLE 3-3. The result of thesimulation execution result in TABLE 3-3 is the first value, which meansthat the simulation execution is successful, and the detail field of thesimulation execution result is the calculation result.

TABLE 3-2 Result Detail Second Exception value code

TABLE 3-3 Result Detail First Calculation value result

In one embodiment, when the operand of the received instructioncomprises a new architecture register, the new architecture register issimulated by the system management memory. For example, when asubsequent-generation processor of the processor 200 comprises a newarchitecture register with a bit width of 1024-bit, the simulator 142may use a continuous 1024-bit storage space in the system managementmemory to simulate the new architecture register. That is, when thereceived instruction accesses the new architecture register, what thesimulator 142 actually accesses is the continuous 1024-bit storage spacein the system management memory.

When the new architecture register is the destination operand of thereceived instruction, the processor 200 stores the operation result ofthe received instruction in the system management memory after executingthe at least one old instruction. In this way, when the processor 200executes another received instruction which is also a new instructionand the new architecture register is the source operand of the anotherreceived instruction, the processor 200 directly use the operationresult stored in the system management memory in the process ofsimulating the execution of the another received instruction. It shouldbe noted that the received instruction and the another receivedinstruction may be continuous (that is, adjacent), or not continuous,and it should not be limited in the disclosure.

In the system management mode, the simulator 142 can only access thesystem management memory, but cannot access the memory (that is, thesystem memory, the same below) in a normal way of accessing the memory.In an embodiment of the present disclosure, a physical memory directaccess interface is provided to implement the operation of accessing thememory in the system management mode. When the received instructioncomprises a memory operand, the memory operand can be accessed throughthe physical memory direct access interface. The steps to access thememory operand through the physical memory direct access interface areas follows.

In the first step, the simulator 142 converts the virtual address of thememory operand into a physical address. Specifically, the simulator 142converts the virtual address of the memory operand into a physicaladdress through the physical memory direct access interface by accessinga page table. The steps of converting a virtual address to a physicaladdress are: 1. reading the base address of the page table stored in thearchitecture register CR3 from the system management memory; 2.simulating page table query process based on the base address of thepage table and the virtual address to obtain the physical address.

In the second step, the simulator 142 reads the value of the memoryoperand according to the physical address through the physical memorydirect access interface, wherein the physical address is not in thesystem management memory. Specifically, the simulator 142, through thephysical memory direct access interface, uses a model specific register(MSR) to read the value of the memory operand according to the physicaladdress. The specific steps are as follows.

In step 1, the simulator 142 writes the address of the model specificregister into a first register (ECX), and writes the physical addressinto a second register (EDX:EAX).

In step 2, the simulator 142 executes a write MSR (WRMSR) instruction tostore the value of the memory operand in the model specific register.Specifically, after the simulator 142 executes the WRMSR instruction,the physical address is written into the model specific register. Then,the processor 200 uses the physical address stored in the model specificregister to load the value of the memory operand from the system memoryto the model specific register by executing a load microinstruction fromthe physical address (ld_phys).

In step 3, the simulator 142 executes the read MSR (RDMSR) instructionto read the value of the memory operand from the model specificregister, and stores the value of the memory operand in the secondregister.

In one embodiment, the next instruction of the received instruction isthe another received instruction. The final instruction in the at leastone old instruction is a jump instruction (jmp) or a call instruction(call). The processor 200 jumps to the another received instructionthrough the jump instruction or the call instruction. The instructionpointer of the another received instruction is: EIP+Length, wherein EIPis the instruction pointer of the received instruction, and Length isthe length of the received instruction.

Then, the simulator 142 executes step S630. In step S630, the simulator142 writes the simulation execution result into the system managementmemory. Specifically, the simulator 142 stores the simulation executionresult generated in step S625 or step S620 into the system managementmemory. As shown above, there are two conditions in the simulationexecution result: one is that the simulation execution is successful,and the other is that the simulation execution failed. The systemmanagement memory comprises an exception vector table, and the structureof the exception vector table is shown in TABLE 4 below. The exceptionvector table comprises two fields: an exception flag and an exceptioncode. When the simulation execution result is stored in the systemmanagement memory, the simulator 142 needs to fill in the exceptionvector table in the system management memory. The following describesthe process of the simulator 142 storing the simulation executionresults of these two situations into the system management memory.

TABLE 4 Exception Exception flag code . . . . . .

When the simulation execution is successful, the simulator 142 sets theexception flag field of the exception vector table in the systemmanagement memory to the first value (as shown in TABLE 4-1 below), andstores the calculation result stored in the detail field of thesimulation execution result in the system management memory. Forexample, when the operation result shows that the value of thearchitecture register ECX is set to 10H (that is, the hexadecimal number10, the same below), the simulator 142 needs to write 10H into thestorage space corresponding to the architecture register ECX in thesystem management memory. When the operation result shows that the valueof the new architecture register is set to 20H, the simulator 142 needsto write 20H into the storage space used to simulate the newarchitecture register in the system management memory. The simulator 142also updates the instruction pointer stored in the system managementmemory to: EIP+Length, so that the instruction pointer points to thenext instruction to be executed, wherein EIP is the instruction pointerof the received instruction, Length is the length of the receivedinstruction. The storage space of the instruction pointer in the systemmanagement memory is the storage space corresponding to the architectureregister EIP. When the processor exits the system management mode, thevalue in the storage space corresponding to the architecture register inthe system management memory is written into the correspondingarchitecture register 260 to send the simulation execution result of thenew instruction to the application 130 or the operating system 120. Thedetails will be described later.

TABLE 4-1 Exception Exception flag code First value . . .

When the simulation execution fails, it means that an exception occurredduring the simulation execution. The simulator 142 sets the exceptionflag field of the exception vector table in the system management memoryto the second value (as shown in TABLE 4-2 below), and writes theexception code stored in the detail field of the simulation executionresult into the exception code field of the exception vector table. Itmay be determined whether the exception is a trap according to theexception code. When the exception is a trap, the simulator 142 updatesthe instruction pointer stored in the system management memory to:EIP+Length, so that the instruction pointer points to the nextinstruction set architecture instruction to be executed, wherein EIP isthe instruction pointer of the received instruction, and Length is thelength of the received instruction stored in the system managementmemory.

TABLE 4-2 Exception Exception flag code Second Exception value code

Then, the simulator 142 executes step S635. In step S635, the simulator142 executes a resume from system management mode (RSM) instruction.After executing the RSM instruction, the processor 200 executes themicrocode handler of the system management mode exit 1144 as shown inFIG. 1, which will be described in detail below with reference withFIGS. 9A˜9B.

FIG. 7 shows a processing flowchart of the conversion program accordingto the first embodiment of the present disclosure. FIG. 7 is aprocessing flowchart of the conversion program 145 shown in FIG. 1.Please refer to FIG. 2 and FIG. 7. As shown in FIG. 7, the conversionprogram 145 obtains the operation code of the received instruction(S705). Then, the conversion program 145 determines whether the receivedinstruction is a new instruction according to the operation code (S710).When the received instruction is a new instruction, the conversionprogram 145 converts the received instruction into at least one oldinstruction (S720), and generates a conversion result (S725). Thedetails are as follows: the conversion program 145 first executes stepS705.

In step S705, the conversion program 145 obtains the operation code ofthe received instruction according to the information of the receivedinstruction. It should be noted that since the received instruction hasnot been decoded at this time, the information of the receivedinstruction does not comprise decoding information such as prefix,escape code, and operation code. According to the description of stepS415 in FIG. 4, in one embodiment, the information of the receivedinstruction only comprises the instruction pointer of the receivedinstruction. In another embodiment, the information of the receivedinstruction comprises the instruction pointer of the receivedinstruction and the machine code of the received instruction. When theconversion program 145 executes the processing flow shown in FIG. 7, theprocessing flow can be divided into the following three cases.

The first case: the information of the received instruction onlycomprises the instruction pointer of the received instruction. When theconversion program 145 decodes the received instruction, the conversionprogram 145 reads and processes one-byte machine code at a timeaccording to the instruction pointer of the received instruction untilthe decoding is completed.

The second case: the information of the received instruction onlycomprises the instruction pointer of the received instruction. Theconversion program 145 first reads all bytes of the machine code of thereceived instruction according to the instruction pointer of thereceived instruction, and then decodes the machine code.

The third case: the information of the received instruction comprisesthe instruction pointer of the received instruction and the machine codeof the received instruction. The conversion program 145 directly decodesthe machine code in the information of the received instruction.

In the first case, the conversion program 145 executes the processingflow shown in FIG. 7. The conversion program 145 first executes stepS705.

In step S705, the conversion program 145 obtains the operation code(opcode) of the received instruction. Specifically, the conversionprogram 145 obtains the operation code of the received instructionaccording to the information of the received instruction. As mentionedabove (step S605 in FIG. 6), the information of the received instructionis read from the system management memory by the simulator 142. Theinformation of the received instruction only comprises the instructionpointer of the received instruction, and the conversion program 145obtains the operation code of the received instruction according to theinstruction pointer of the received instruction. In detail, theconversion program 145 reads the first byte of the machine code of thereceived instruction from the memory according to the instructionpointer of the received instruction, and then determines the operationcode of the received instruction according to the read byte (that is,the first byte). When the conversion program 145 cannot determine theoperation code of the received instruction according to the first byteof the machine code, the conversion program 145 reads the second byte ofthe machine code, and then determines the operation code of the receivedinstruction according to the read byte (i.e., the first 2 bytes). And soon, until the operation code of the received instruction is determined.It should be noted that when the received instruction comprises a prefixand/or an escape code, the conversion program 145 may first obtain theprefix and/or the escape code of the received instruction, and thenobtain the operation code of the received instruction. In oneembodiment, the conversion program 145 reads the machine code from thememory according to the instruction pointer of the received instructionthrough the physical memory direct access interface as described above.After the conversion program 145 obtains the operation code, theconversion program 145 executes step S710.

Next, in step S710, the conversion program 145 determines whether thereceived instruction is a new instruction. Specifically, the conversionprogram 145 determines whether the received instruction is a newinstruction according to the operation code of the received instruction.For example, the operation code of the new instruction supported by theprocessor 200 may be stored in a lookup table. The conversion program145 may check whether the operation code is stored in the lookup table.When the operation code is stored in the lookup table, it means that thereceived instruction is a new instruction, and the determination resultis “Yes”; otherwise, the determination result is “No”. In oneembodiment, the lookup table is stored in the system management memory.In one embodiment, the conversion program 145 determines whether thereceived instruction is a new instruction according to the escape codeand the operation code of the received instruction at the same time.

When the received instruction is not a new instruction (thedetermination result of step S710 is “No”), it means that the receivedinstruction is an unrecognizable instruction, and the conversion program145 executes step S725 to generate the conversion result shown in TABLE2-1 below. As shown in the following TABLE 2-1, the value of the resultfield of the conversion result is the second value, which indicates thatthe conversion failed. The content field of the conversion result is theexception code #UD (the value is 6) of the unknown instructionexception.

TABLE 2-1 Result Content Second #UD value

When the received instruction is a new instruction (the determinationresult of step S710 is “Yes”), the conversion program 145 executes stepS712. In step S712, the conversion program 145 determines whether thereis a decoding exception. Specifically, as described above (step S605 inFIG. 6), the simulation program 142 reads the operating environmentinformation at the time when the processor 200 executes the receivedinstruction from the system management memory, wherein the operatingenvironment information comprises the operating mode of the processor200. The conversion program 145 determines whether the receivedinstruction can be executed in the operating environment. For example,when the operating mode is the real mode and the received instructioncannot run in the real mode, the determination result of step S712 is“Yes”. When the received instruction can run in the real mode, thedetermination result of step S712 is “No”.

In one embodiment, the operation code of the new instruction and theoperating environment supporting the new instruction are stored in alookup table. The conversion program 145 can find out under whichoperating environments the received instruction can run, through thelookup table, according to the operation code of the receivedinstruction. In another embodiment, the lookup table is stored in thesystem management memory.

When the conversion program 145 determines that there is a decodingexception (the determination result of step S712 is “Yes”), theconversion program 145 executes step S725 to generate the conversionresult shown in the following TABLE 2-2. As shown in the following TABLE2-2, the value of the result field of the conversion result is thesecond value, which means the conversion failed. The content field ofthe conversion result is the exception code #UD (the value is 6) of theunknown instruction exception.

TABLE 2-2 Result Content Second #UD value

When the conversion program 145 determines that there is no decodingexception (the determination result of step S712 is “No”), step S715 isexecuted. In step S715, the conversion program 145 obtains otherdecoding information of the received instruction. Specifically, theconversion program 145 continues to read the machine code of thereceived instruction from the memory byte by byte, decodes the machinecode while reading the machine code until the conversion program 145obtains other decoding information of the received instruction, andcalculates the length of the received instruction, wherein the otherdecoding information comprises the operand mode (ModR/M), the sourceoperand and the destination operand, and so on. Those skilled in the artknow that only after the conversion program completes the decoding ofthe received instruction, the conversion program calculates the lengthof the received instruction. Then, the conversion program 145 executesstep S720.

In step S720, the conversion program 145 converts the receivedinstruction into at least one old instruction. Specifically, theconversion program 145 may convert the received instruction into atleast one old instruction by using a lookup table. For example, at leastone old instruction corresponding to the received instruction may bestored in a lookup table first. Then, the conversion program 145 obtainsthe at least one old instruction from the lookup table according to theoperation code of the received instruction. In one embodiment, when thereceived instruction comprises an escape code, the conversion program145 obtains the at least one old instruction from the lookup tableaccording to the escape code and operation code of the receivedinstruction. In another embodiment, the conversion program 145 obtainsthe at least one old instruction from the lookup table according to theescape code, the operation code, and the operand mode of the receivedinstruction.

It should be noted that since the at least one old instruction obtainedfrom the lookup table does not comprise the other decoding informationsuch as the source operand and/or the destination operand of thereceived instruction, the other decoding information is needed to bewritten into the at least one old instruction, so that the at least oneold instruction may be used to simulate the execution of the receivedinstruction. For example, the conversion program 145 writes the specificvalues of the source operand and/or the destination operand of thereceived instruction into the corresponding location in the at least oneold instruction. Then, the processor 200 can simulate the execution ofthe new instruction by executing the at least one old instruction. Inone embodiment, the conversion program 145 writes the other decodinginformation into the at least one old instruction according to theprefix of the received instruction.

In one embodiment, the lookup table is stored in a basic input outputsystem (BIOS). Those skilled in the art know that the system 100 forexecuting new instructions can execute the basic input output systemwhen the system 100 for executing new instructions is started up. Thebasic input output system comprises codes for initializing the systemmanagement mode. When the system 100 executes the codes for initializingthe system management mode, the lookup table is loaded into the systemmanagement memory. Then, the conversion program 145 can obtain the atleast one old instruction from the lookup table according to theoperation code of the received instruction.

In another embodiment, the conversion program 145 stores the at leastone old instruction in a memory or a cache. When the processor 200executes another instruction and the another received instruction is anew instruction, the conversion program 145 determines whether thereceived instruction and the another received instruction are the sameinstruction. When the received instruction and the other receivedinstruction are the same instruction, the conversion program 145directly obtains the at least one old instruction from the memory or thecache.

Then, the conversion program 145 executes step S725 to generate theconversion result shown in the following TABLE 2-3. As shown in TABLE2-3, the value of the result field of the conversion result is the firstvalue, which means the conversion program successfully converts thereceived instruction. The content field of the conversion result is thelength of the received instruction and the at least one old instruction.

TABLE 2-3 Result Content First The length of the received valueinstruction and at least one old instruction

The process by which the conversion program 145 executes the processingflow of FIG. 7 in the second case is described as follows. In the secondcase, the process of steps S710, S712, S720 and S725 executed by theconversion program 145 is the same as that in the first case, so thedetails related to steps S710, S712, S720 and S725 will be omitted.Steps S705 and S715 are described below.

In the second case, unlike the first case, in step S705, the conversionprogram 145 first reads the complete machine code of the receivedinstruction from the memory according to the instruction pointer of thereceived instruction. Then, the conversion program 145 decodes themachine code to obtain the operation code of the received instruction.Next, in step S715, the conversion program 145 also decodes the machinecode read in step S705 to obtain other decoding information of thereceived instruction. The other processing in the second case is thesame as that in the first case, so the details will be omitted.

It should be noted that when the conversion program 145 reads themachine code according to the instruction pointer of the receivedinstruction, since the conversion program 145 does not yet know thelength of the received instruction, the conversion program 145 needs toread the machine code of sufficient length. For example, it is assumedthat the length of the longest new instruction among the newinstructions that can be processed by the processor 200 is 15 bytes.Then, the conversion program 145 needs to read the machine code whoselength is at least 15 bytes.

The process by which the conversion program 145 executes the processingflow of FIG. 7 in the third case is described as follows. In the thirdcase, the process of steps S710, S712, S720 and S725 executed by theconversion program 145 is the same as that in the second case, so thedetails related to steps S710, S712, S720 and S725 will be omitted.Steps S705 is described below.

In the third case, unlike the second case, in step S705, the conversionprogram 145 directly decodes the machine code in the information of thereceived instruction to obtain the operation code of the receivedinstruction. The other processing in the third case is the same as thatin the second case, so the details will be omitted.

FIG. 8 shows an example of processing unknown instructions in the systemmanagement mode according to the first embodiment of the presentdisclosure. FIG. 8 is a processing flow showing how to process unknowninstructions as shown in FIGS. 6 and 7 in the form of pseudo code, whichis an implementation of the simulator.

As shown in FIG. 8, lines 1-25 are the code included in the simulator'smain function, simulator_start. Lines 27-36 are the code included in thedecoding function, check_decode_excep. Lines 38-47 are the code includedin the simulation function of the new instruction function,Unsupport_X_handle, wherein the code includes at least one oldinstruction corresponding to the received instruction described above.The main function, simulator_start, is described below first.

In the main function, simulator_start, the third line of code isexecuted first. The third line of code is used to complete the functionof step S605 in FIG. 6, that is, the processor 200 establishes asimulation operating environment. In the third line of code, theprocessor 200 establishes a simulation operating environment through thefunction, setup_simulator_env. After executing the third line of code,the processor 200 stores the emulation flag, the information of thereceived instruction, the operating environment information of thereceived instruction, and the information of the architecture registerread from the system management memory into the variable, env. Forexample, in the 4th line of code, the value of the emulation flag isaccessed through env.emulation_flag. The 4th line of code completes thefunction of step S610 in FIG. 6, that is, the processor 200 determineswhether the emulation flag is the first value. When the determinationresult of the 4th line of code is that the emulation flag is not thefirst value, the 5th line of code is executed. The 5th line of codeexecutes the function of step S645 in FIG. 6, that is, the processor 200executes the normal processing flow of the system management mode. Inthe 5th line of code, the processor 200 executes the normal processingflow of entering the system management mode through the function,exit_to_normal_SMM. When the determination result of the 4th line ofcode is that the emulation flag is the first value, the 8th line of codeis executed to define the variable, inst_emu, as the outgoing parameterof the decoding function, check_decode_excep, in the 9th line of code(described later). Then, the 9th line of code is executed.

The code in lines 9-15 executes the function of step S615 in FIG. 6,that is, the processor 200 converts the received instruction through aconversion program and generates a decoding result. Specifically, theprocessor 200 first executes the 9th line of code, and obtains decodinginformation such as the operation code of the received instructionthrough the decoding function, check_decode_excep, wherein the decodinginformation is stored in the outgoing parameter, inst_emu. Then, theprocessor 200 executes the 10th line of code to determine whether thedecoding is successful. In the 10th line of code, the processor 200determines whether the decoding is successful according to the decodingresult, decode_excep. When the decoding fails (it means that theconversion has failed), the processor 200 executes the 11th line ofcode. The 11th line of code executes the function of step S630 in FIG.6, that is, the processor 200 writes the simulation execution result ofthe conversion failure into the system management memory. In the 11thline of code, the processor 200 writes the simulation execution resultof the conversion failure into the system management memory through thefunction, set_exception. After the 11th line of code is executed, the12th line of code is executed, and then the processor 200 jumps to the23rd line of code. In the 12th line of code, the processor 200 jumps tothe location of the label, out, (that is, the 23rd line) through theinstruction, goto. Then, the processor 200 continues the execution fromthe 23rd line of code. Since there is only one label, out, in the 23rdline of code and there is no code to be executed, the processor 200executes the 24th line of code. The 24th line of code executes thefunction of step S635 in FIG. 6, that is, the processor 200 executes theresume from system management mode instruction. In the 24th line ofcode, the processor 200 executes the resume from system management modeinstruction through the function, execute_rsm. Then, the processor 200executes the microcode of the system management mode exit 1144 as shownin FIG. 1. When the determination result of the 10th line of code isthat the decoding is successful, the 15th line of code is executed. The15th line of code executes the function of step S720 in FIG. 7, that is,the processor 200 converts the received instruction into at least oneold instruction according to the information of the receivedinstruction. As shown in FIG. 8, in the 15th line of code, the at leastone old instruction is found from the table, op_mapping, by using theoperation code of the received instruction. The function pointer,routine, is used to represent the at least one old instruction, and thevalue of routine is the address of the function, Unsupport_X_handle.Then, the 16th line of code is executed.

The 16th line of code executes the function of step S625 in FIG. 6, thatis, the processor 200 executes at least one old instruction. When thefunction, routine, is executed, the processor 200 actually executes thesimulation function, Unsupport_X_handle, (which will be described indetail later). After the function, routine, is executed, a value,runtime_excep, is returned. Then, the 18th to 19th lines of code areexecuted. The 18th to 19th lines of code execute the function of stepS630 in FIG. 6, that is, the processor 200 determines whether there is aruntime exception. When there is a runtime exception, the processor 200writes the simulation execution result of the runtime exception into thesystem management memory. In the 18th line of code, the processor 200determines whether there is a runtime exception according to the valueof the return value, runtime_excep. When there is a runtime exception,the 19th line of code is executed. In the 19th line of code, theprocessor 200 stores the simulation execution result of the runtimeexception into the system management memory through the function,set_exception. Then, the processor 200 executes the 20th line of codeand jumps to the 23rd line of code through the instruction, goto. Asmentioned above, the processor 200 may execute the 24th line of codenext. The function of the 24th line of code has been described before,so the details related to the function of the 24th line of code will beomitted.

The decoding function, check_decode_excep, is described below.

In the decoding function, check_decode_excep, the 29th to 30th lines ofcode are first executed to obtain the operation code of the receivedinstruction (step S705 in FIG. 7). In 29th line of code, the processor200 reads the machine code, machine_code, of the received instructionthrough the function, read_instruction. Here, the processor reads themachine code, machine_code, with the byte length, code_len, from thememory according to the instruction pointer, ip, of the receivedinstruction (that is, the second case mentioned in the previousexplanation of FIG. 7), and the value of code_len can be 15. In 30thline of code, the processor 200 decodes the machine code, machine_code,through the function, decode_opcode, to obtain the operation code,opcode, of the received instruction. In the 31st line of code, theprocessor 200 determines whether the received instruction is a newinstruction according to the opcode through the function, is_emulate_op,(step S710 in FIG. 7). When the received instruction is not a newinstruction, the processor 200 executes the code on the 32nd line ofcode, and returns decoding exception information to the main function,simulator_start, through the instruction, return. When the receivedinstruction is a new instruction, the processor 200 first executes the33rd line of code, and stores the opcode in the outgoing parameter,inst_emu, executes the 34th line of code to obtain other decodinginformation of the received instruction (Step S715 in FIG. 7), and storethe other decoding information in the outgoing parameter, inst_emu.Finally, the processor 200 executes the 35th line of code to return thedecoding success information to the main function, simulator_start,through the instruction, return. The main function, simulator_start, canobtain the opcode and the other decoding information, operands, of thereceived instruction through the outgoing parameter, inst_emu.

The simulation function, Unsupport_X_handle, is described below.

In the simulation function, Unsupport_X_handle, the 40th to 41st linesof code are first executed. The 40th to 41st lines of code execute theoperation of reading the value of the operand and storing the value ofthe read operand in the array, op. In the 41st line of code, theprocessor completes the operation of reading operands through thefunction, read_op. Specifically, the function, read_op, obtains thevalue of the operand from the variable, env, described above. The 42ndline of code executes step S625 in FIG. 6, that is, the processor 200executes the at least one old instruction. In other words, the processor200 simulates the execution of the received instruction. In the 42ndline of code, op represents the operand of the received instruction, and‘operate with op’ represents that the value of the operand of thereceived instruction is written into the at least one old instruction,and the at least one old instruction is executed. Then, the 43rd line ofcode is executed. The 43rd line of code executes step S630 in FIG. 6,that is, the processor 200 writes the simulation execution result(comprising simulation execution results that generate runtimeexceptions and simulation execution results that do not generate runtimeexceptions) into the system management memory. Specifically, in the 43rdline of code, the processor 200 stores the simulation execution resultinto the system management memory through the function,write_result_to_SMRAM. The 44rd line of code determines whether aruntime exception occurs when the 42nd line of code is executed. When aruntime exception occurs, the 45th line of code is executed, and theexception information is sent to the main function; otherwise, the 46thline of code is executed, and the correct execution information is sentto the main function. In the 45th and 46th lines of code, the processor200 sends the exception information or the correct execution informationto the main function, simulator_start, through the instruction, return.

FIGS. 9A˜9B show a flowchart of exiting the system management modeaccording to the first embodiment of the present disclosure. FIGS. 9A to9B are the processing flow of the microcode handler corresponding to thesystem management mode exit 1144 shown in FIG. 1. Please refer to FIGS.2, 9A and 9B. As shown in FIGS. 9A to 9B, when exiting the systemmanagement mode, the processor 200 determines whether the emulation flagis the first value (S901). When the determination result is “Yes”, theprocessor 200 resets the emulation flag (S904), and determines whetherthere is an exception in the simulation execution result (S905). Theprocessor 200 executes the operation of exiting the system managementmode according to whether there is an exception in the simulationexecution result and the type of the exception. The detailed descriptionis as follows: the processor 200 first executes step S901.

In step S901, the processor 200 determines whether the emulation flag isthe first value. Specifically, the processor 200 reads the emulationflag from the system management memory (As shown in the description ofstep S520 in FIG. 5 above, the emulation flag is stored in the systemmanagement memory), and then determines whether the emulation flag isthe first value. When the emulation flag is not the first value, theprocessor 200 executes step S903. In step S903, the processor 200executes the normal processing flow of exiting the system managementmode. The normal processing flow of exiting the system management modeis the common knowledge of those skilled in the art, so the details willbe omitted. When the emulation flag is the first value, the processor200 executes step S904.

In step S904, the processor 200 resets the emulation flag. Specifically,the processor 200 sets the emulation flag in the microarchitectureregister 220 and emulation flag in the system management memory to thesecond value. After resetting the emulation flag, the processor 200executes the normal processing flow of the system management mode in thesubsequent execution process when a normal system management interruptoccurs. Then, the processor 200 executes step S905.

In step S905, the processor 200 determines whether there is an exceptionin the simulation execution result. Specifically, the processor 200reads the exception vector table shown in TABLE 4 from the systemmanagement memory. When the value of the field of the exception flag inthe exception vector table is the first value, it means that theexception exists in the simulation execution result, and thedetermination result is “Yes”. When the value of the field of theexception flag in the exception vector table is the second value, itmeans that there is no exception in the simulation execution result, andthe determination result is “No”. When the determination result is “No”,the processor 200 executes step S907.

As shown in FIG. 9B, in step S907, the processor 200 stores thesimulation execution result stored in the system management memory intothe architecture register. As described above, in step S630 in FIG. 6,the processor 200 has written the simulation execution result of thereceived instruction into a region corresponding to the architecturalregister in the system management memory. In this step, the processor200 stores the values in the region corresponding to the architecturalregister in the system management memory into the architectural register260. In this way, this is equivalent to the processor 200 has executedthe received instruction.

When the destination operand of the received instruction is a newarchitecture register, the processor 200 cannot store the values storedin the region of the system management memory for simulating the newarchitecture register since the architecture register 260 of theprocessor 200 does not comprise the new architecture register. Asmentioned above, when the processor 200 simulates another newinstruction and the operand of the another new instruction is also thenew architecture register, the processor 200 directly use the valuesstored in the region of the system management memory for simulating thenew architecture register to simulate the execution of the another newinstruction.

Then, the processor 200 executes step S909. In step S909, the processor200 enables the interrupt. For example, the processor 200 sets the IFflag to enable maskable interrupts, sets the TF flag to enablesingle-step interrupts, and sets DR7 to enable breakpoint interrupts.Then, the processor 200 executes step S911.

In step S911, the processor 200 generates a notification of exitingsystem management mode (Deassert #smmact) to notify the chipset that theprocessor 200 has exited the system management mode. Then, the processor200 executes step S913 to exit the system management mode.

As shown in FIG. 9A, when the processor 200 determines that there is anexception in the simulation execution result in step S905, step S915 isexecuted.

In step S915, the processor 200 determines whether the exception is atrap. Specifically, the processor 200 determines whether the exceptionin the simulation execution result is a trap according to the exceptionflag and the exception code in the exception vector table read from thesystem management memory in step S905. For example, when the exceptionflag is the first value and the exception code is 3 (the content inTABLE 4 is shown in TABLE 4-3 below), it indicates an overflowexception. The type of overflow exception is a trap, so thedetermination result is “yes”. When the exception flag is the firstvalue and the exception code is 0 (the content in TABLE 4 is shown inTABLE 4-4 below), it indicates a division error exception. The divisionerror exception is a fault, not a trap, so the determination result is“No”.

TABLE 4-3 Exception Exception flag code First value 3

TABLE 4-4 Exception Exception flag code First value 0

When the determination result of step S915 is “No”, the processor 200executes steps S917, S919, S921, and S923, wherein step S917, step S919and step S921 are the same as step S909, step S911 and step S913respectively, so the details related to step S917, step S919 and stepS921 will be omitted. Step S923 is described below.

In step S923, the processor 200 executes a microcode handler of theexception. Specifically, the processor 200 determines whether anexception has occurred according to the exception flag in the exceptionvector table stored in the system management memory. When an exceptionoccurs, the processor 110 executes the microcode handler of theexception according to the exception code stored in the exception vectortable. That is, the microcode handler of the exception corresponding tothe exception code is executed. For example, when the exception flag inthe exception vector table stored in the system management memory is thefirst value, it indicates that the exception exists in the simulationexecution result. When the exception code in the exception vector tableis 0, it means that the exception is a division error, and the processor200 may execute a microcode handler of the division error.

In step S915, when the determination result is “Yes”, that is, when theexception of the simulation execution result is a trap, the processor200 executes steps S925, S927, S929, and S933 shown in FIG. 9B, whereinsteps S925, S927, and S929 are the same as steps S907, S909, and S911,respectively, so the details related to step S925, S927, and S929 willbe omitted. Step S933 is described below.

In step S933, the processor 200 executes a microcode handler of theexception. For example, when there is an exception in the simulationexecution result and the exception is an overflow exception, theprocessor 200 executes a microcode processing handler for the overflowexception. In the actual operation of exiting the system management modethrough the system management interrupt exit 1144 shown in FIGS. 9A and9B, after the resume from system management mode (RSM) instruction iscalled, those skilled in the art may add some microcodes, for storingthe simulation execution result from the system management memory intothe architecture register, to the microcodes corresponding to the resumefrom system management mode, so as to transmit the simulation executionresult to the application program 130 or the operating system 120. Sincethese microcodes are different depending on the processor version, thoseskilled in the art may write corresponding microcodes according toactual conditions.

It should be noted that, in the first embodiment, the microarchitectureregister 220 is a register that already exists in the processor 200.Therefore, in the first embodiment of the present disclosure, the newinstructions may be executed on the previous-generation processorwithout modifying the hardware structure of the processor. Therefore, byupgrading the microcodes in the first embodiment of the presentdisclosure, the processor that has been produced can obtain the functionof executing the new instruction.

[Second Embodiment]

FIG. 10 is a schematic diagram of a system 1000 for executing newinstructions according to the second embodiment of the presentdisclosure. The difference from the first embodiment shown in FIG. 1 isthat the conversion program 145 in the system 1000 for executing newinstructions shown in FIG. 10 runs directly on the processor 110 in thesame execution mode as the new instructions. In addition, since theconversion program 145 in the second embodiment runs in the sameexecution mode as the new instructions, the processor does not need toswitch the operation mode when executing the conversion program 145. Thedifference between the second embodiment and the first embodiment aredescribed in detail below.

As shown in FIG. 10, when the instruction 118 is an unknown instruction132, the processor 110 executes a microcode handler for handling theunknown instruction exception. In the microcode handler for handling theunknown instruction exception, the conversion program 145 is directlycalled (as shown by the solid arrow 2 in FIG. 10). The conversionprogram 145 determines whether the unknown instruction 132 is a newinstruction. When the unknown instruction 132 is a new instruction, theconversion program 145 converts the new instruction into at least oneold instruction, and sends the at least one old instruction to themicrocode handler that handles the unknown instruction exception (asshown by the solid arrow 6 in FIG. 10). The microcode handler thathandles the unknown instruction exception receives the at least one oldinstruction, and instructs the processor 110 to execute the at least oneold instruction through a call instruction (call) or a jump instruction(jmp).

FIG. 11 is a structural diagram of the processor according to the secondembodiment of the present disclosure. The functions of the componentswith the same names in FIG. 11 and FIG. 2 are the same, so the detailsrelated to the functions of the components will be omitted.

It should be noted that, as shown in FIG. 11, the processor 1100 on theleft of the dashed line is a structural diagram of the processor 110shown in FIG. 10. The conversion program 145 on the right of the dashedline runs on the processor 1100 in the same execution mode as the newinstruction (that is, the processor does not need to switch theexecution mode). The conversion program 145 may be stored in theinterrupt preprocessing unit 112 in the processing core of the processor1100. In another embodiment, the conversion program 145 may be stored inan uncore of the processor 1100. Therefore, all the processing cores ofthe processor 1100 can share the conversion program 145.

FIG. 12 is a flowchart showing the execution of the new instructionaccording to the second embodiment of the present disclosure. Theprocessing flow shown in FIG. 12 can be executed by the processor 1100in FIG. 11. As shown in FIG. 12, the processor 1100 receives aninstruction (S1205), and when the received instruction is an unknowninstruction, the processor 1100 generates an unknown instructionexception (S1210). In response to the unknown instruction exception, theprocessor 1100 determines whether the received instruction is a newinstruction through a conversion program (S1215). When the receivedinstruction is a new instruction, the processor 1100 converts thereceived instruction into at least one old instruction through theconversion program (S1220). Finally, the processor 1100 executes the atleast one old instruction in the same execution mode as the receivedinstruction (S1225). Steps S1205 and S1210 in FIG. 12 are the same assteps S305 and S310 in FIG. 3, so the details related to steps S1205 andS1210 will be omitted. The difference between steps S320 and S325 inFIG. 3 and steps S1220 and S1225 in FIG. 12 is that steps S320 and S325in FIG. 3 run in the system management mode, while steps S1220 and S1225in FIG. 12 run in the same execution mode as the received instruction.The functions performed by steps S320 and S325 in FIG. 3 are the same asthose performed by steps S1220 and S1225 in FIG. 12, so the detailsrelated to steps S1220 and S1225 will be omitted. Only step S1215 isdescribed below.

In step S1215, in response to the unknown instruction exception, theprocessor 1100 determines whether the received instruction is a newinstruction through a conversion program. Specifically, after theinstruction retiring unit 245 generates an unknown instructionexception, the processor 1100 executes a microcode handler for handlingthe unknown instruction exception. In the microcode handler for handlingunknown instruction exceptions, the processor 1100 sends the informationof the received instruction and operating environment information to theconversion program 145. The conversion program 145 determines whetherthe received instruction is a new instruction according to theinformation of the received instruction. As for how the conversionprogram 145 determines whether the received instruction is a newinstruction, the details have been described in the first embodiment, sothe details will be omitted.

FIG. 13 is a flowchart showing the processing of the receivedinstruction according to the second embodiment of the presentdisclosure. Steps S1305, S1310, and S1325 in FIG. 13 are the same assteps S405, S410, and S435 in FIG. 4, so the details related to stepsS1305, S1310, and S1325 will be omitted. Step S1320 is described below.

In step S1320, the processor 1100 in FIG. 11 processes the receivedinstruction. Specifically, when the received instruction is an unknowninstruction (the determination result of step S1310 is “Yes”), theprocessor 1100 executes a microcode handler of the unknown instructionexception. In the microcode handler for handling the unknown instructionexception, the processor 1100 processes the unknown instruction throughthe conversion program 145 (which will be described in detail later withreference to FIG. 14).

FIG. 14 is a flow chart of processing the received instruction in amicrocode handler for handling unknown instruction exceptions accordingto the second embodiment of the present disclosure. As shown in FIG. 14,the processor 1100 in FIG. 11 obtains the information of the receivedinstruction (S1405), converts the received instruction through theconversion program 145, and generates a conversion result (S1410). Whenthe conversion program successfully converts the received instruction(the determination result of step S1415 is “Yes”), the processor 1100obtains at least one old instruction from the conversion result, andexecutes the at least one old instruction (S1420). The detaileddescription is as follows: the processor 1100 first executes step S1405.

In step S1405, the processor 1100 obtains the information of thereceived instruction in the microcode handler of the unknown instructionexception. The information of the received instruction comprises theinstruction pointer of the received instruction. It should be noted thatsince the received instruction has not been decoded at this time, theinformation of the received instruction does not comprise the decodinginformation such as prefix, escape code, and operation code. When themicrocode handler of the unknown instruction exception is executed, theoperating environment of the processor 1100 does not change since theprocessor 1100 does not need to perform mode conversion. Therefore, in amicrocode handler of the unknown instruction exception, the operatingenvironment information of the processor 1100 can be directly obtained,wherein the operating environment information is the operatingenvironment information of the received instruction. Then, step S1410 isexecuted.

In step S1410, the processor 1100 converts the received instructionthrough the conversion program 145, and generates a conversion result.As for how to convert the received instruction through the conversionprogram 145, the processing procedure is the same as that in the firstembodiment, so the details related to the processing procedure will beomitted. Step S1415 is the same as step S620 in FIG. 6, so the detailsrelated to step S1415 will be omitted. Steps S1420 and S1425 aredescribed below.

When the conversion program 145 successfully converts the receivedinstruction (“Yes” in step S1415), the processor 1100 executes stepS1420. In step S1420, the processor 1100 obtains at least one oldinstruction from the conversion result, and executes the at least oneold instruction. In addition, the processor 1100 may also obtain thelength of the received instruction from the conversion result. In oneembodiment, the next instruction of the received instruction is anotherreceived instruction. The final instruction in the at least one oldinstruction is a jump instruction (jmp) or a call instruction (call),and the processor 1100 jumps to the another received instruction throughthe jump instruction or the call instruction. The instruction pointer ofthe another received instruction is: EIP+Length, wherein EIP is theinstruction pointer of the received instruction, and Length is thelength of the received instruction.

When the conversion program 145 fails to convert the receivedinstruction (“No” in step S1415), the processor 1100 executes stepS1425. In step S1425, the processor 1100 handles the exception.Specifically, when any exception occurs when the conversion program 145converts the received instruction, it will cause the conversion program145 to fail to convert the received instruction. In the microcodehandler of the interrupt preprocessing unit 112 for processing theunknown instruction exception, an exception code is obtained from thecontent field of the conversion result. Then, the microcode handler thathandles the exception of the unknown instruction generates an exceptioncorresponding to the exception code. In response to the exceptioncorresponding to the exception code, the processor 1100 executes thecorresponding microcode handler to handle the exception.

The processing flow of the conversion program in the second embodimentis the same as the processing flow of the conversion program in FIG. 7in the first embodiment, so the details related to the processing flowof the conversion program will be omitted.

In summary, the difference from the first embodiment is that in thisembodiment, when the processor 1100 executes an unknown instruction, theprocessor 1100 directly executes the conversion program 145 in the sameexecution mode as the unknown instruction. The conversion program 145determines whether the unknown instruction is a new instruction. Whenthe unknown instruction is a new instruction, the conversion program 145converts the new instruction into at least one old instruction. Then,the processor 1100 executes the at least one old instruction in the sameexecution mode as the unknown instruction. Compared with the firstembodiment, in this embodiment, the processor does not need to switchthe execution mode, so the efficiency of simulating new instructions ishigher.

[Third Embodiment]

FIGS. 15A to 15B are schematic diagrams showing the system 1500 forexecuting new instructions according to the third embodiment of thepresent disclosure. The third embodiment is different from the firstembodiment shown in FIG. 1 and the second embodiment shown in FIG. 10 inthat the conversion program 145 in the system 1500 for executing newinstructions is executed by the kernel driver 150 in the operatingsystem 120. The conversion program 145 may be located at inside (asshown in FIG. 15A) or outside (as shown in FIG. 15B) of the kerneldriver 150. Please refer to FIG. 11 and FIGS. 15A to 15B, when theprocessor 1100 determines that the instruction 118 is an unknowninstruction 132, the processor 1100 generates an unknown instructionexception. In response to the unknown instruction exception, theprocessor 1100 executes a microcode handler of the unknown instructionexception. In the microcode handler of the unknown instructionexception, the processor 1100 calls the kernel driver 150, and sends theinformation of the unknown instruction 132 and the operating environmentinformation to the kernel driver 150 at the same time. The kernel driver150 processes the received instruction through the conversion program145.

In one embodiment, in the microcode handler of the unknown instructionexception, the processor 1100 calls the kernel driver 150 through auser-defined interrupt service program (Developers of the interruptservice program may call the user-defined interrupt service programthrough the user-defined interrupt vector #NE (Non-support instructionEmulator), wherein the user-defined interrupt vector #NE is a reservedcode in the interrupt vector table). It should be noted that when theinterrupt service program calls the kernel driver 150, the processor1100 must send the information of the unknown instruction 132(comprising the instruction pointer, etc.) and the operating environmentinformation to the kernel driver 150, or send the storage address of theinformation of the unknown instruction 132 and the operating environmentinformation to the kernel driver 150. Furthermore, the interrupt serviceprogram used by the kernel driver 150 (the interrupt service programcorresponding to the user-defined interrupt vector #NE) may be stored inthe microcode in the interrupt preprocessing unit 112 and be called bythe interrupt preprocessing unit 112 (the interrupt preprocessing unit112 can be constructed with a state machine or a combinational logiccircuit). In one embodiment, the kernel driver 150 processes the unknowninstruction 132 through the conversion program 145, by calling theoperating system 120 through a system call to execute the kernel driver150. For example, the kernel driver 150 is used as a callback function,and the information of the unknown instruction 132 and the operatingenvironment information are sent to the kernel driver 150 as parameters.When the unknown instruction 132 is a new instruction, the kernel driver150 returns at least one old instruction to the processor 1100 afterprocessing the unknown instruction 132 through the conversion program145. In addition, the kernel driver 150 is called either through aninternal interrupt or a trap. For example, the designer of the processor1100 defines an interrupt vector #NE to enter the kernel of theoperating system and call the kernel driver 150, and those skilled inthe art should know the technical details of this part, so the detailsof this part will be omitted. In one embodiment, the process of sendingthe information of the unknown instruction 132 and the operatingenvironment information in the microcode handler of the unknowninstruction exception is: the information of the unknown instruction 132and the operating environment information are pushed into the stack, andthen the kernel driver 150 obtains the information of the unknowninstruction 132 and the operating environment information from thestack.

In another embodiment, the interrupt service program in the operatingsystem that handles the exception of the unknown instruction may bemodified to directly call the kernel driver 150 to realize theprocessing of the unknown instruction 132. In the modified interruptservice program that handles the exception of the unknown instruction,the information of the unknown instruction 132 and the operatingenvironment information may be read first, and the information of theunknown instruction 132 and the operating environment information aretransmitted to the kernel driver 150. In this embodiment, there is noneed to modify the hardware and/or microcode of the processor, justmodify the interrupt service program in the operating system thathandles the exception of the unknown instruction to realize theprocessing of the unknown instruction as described above. It is quiteconvenient to implement. In actual operation, those skilled in the artcan modify the interrupt service program that handles the exception ofthe unknown instruction to add the function of reading the informationof the unknown instruction 132 and the operating environmentinformation, and calling the kernel driver 150. Since the interruptservice programs for handling the exception of the unknown instructionvary depending on the version of the operating system and/or theprocessor, those skilled in the art may write corresponding codesaccording to actual conditions.

FIG. 16 is a flowchart of processing a received instruction according toanother embodiment of the present disclosure. Steps S1605, S1610, andS1625 in FIG. 16 are the same as steps S1305, S1310, and S1325 in FIG.13 of the third embodiment, so the details related to steps S1605,S1610, and S1625 will be omitted. The following describes step S1620.

Please refer to FIG. 11, FIGS. 15A˜15B, and FIG. 16. The processing flowshown in FIG. 16 may be executed by the processor 1100 in FIG. 11. Instep S1620, the processor 1100 processes the received instruction.Specifically, when the received instruction is an unknown instruction,in the microcode handler of the unknown instruction exception, theprocessor 1100 calls the conversion program 145 to process the receivedinstruction through the kernel driver 150 of the operating system 120.It should be noted that, compared with this embodiment, in step S1320 inFIG. 13 of the second embodiment, when the received instruction is anunknown instruction, the processor 1100 directly processes the receivedinstruction through the conversion program 145 in the microcode handlerof the unknown instruction exception.

In one embodiment, the conversion program 145 is a driver or applicationprogram of the operating system 120. Other processing procedures in thethird embodiment are the same as those in the second embodiment, so thedetails related to the processing procedures will be omitted.

In summary, the difference from the second embodiment is that in thisembodiment (the third embodiment), when the processor 1100 executes anunknown instruction, the microcode handler of the unknown instructionexception executes the kernel driver 150 of the operating system 120 tocontinue processing the new instructions. Compared with the secondembodiment, in this embodiment, the kernel driver of the operatingsystem is used to convert the new instructions through the conversionprogram. Compared with updating the hardware of the processor and/or themicrocode in the processor, updating the kernel drivers and conversionprograms are more convenient and faster, thereby improving developmentefficiency.

[Fourth Embodiment]

FIG. 17 is a schematic diagram of a system 1700 for executing newinstructions according to the fourth embodiment of the presentdisclosure. Similar to the third embodiment, in this embodiment (fourthembodiment), the conversion program 145 in the system 1700 for executingnew instructions is also called by the kernel driver 150 in theoperating system 120. The difference is that, in this embodiment, theconversion program 145 runs on a dedicated processing core 190. Thekernel driver 150 sends the information of the unknown instruction 132and the operating environment information to the conversion program 145through a polling or doorbell mechanism. The conversion program 145 alsoneeds to send the conversion result to the kernel driver 150 through thepolling or doorbell mechanism. The following will separately describehow to transfer data between the kernel driver 150 and the conversionprogram 145 through the polling or doorbell mechanism.

The polling mechanism is first described below. Referring to FIGS. 11and 17, in one embodiment, the designer of the processor 1100 may set atransmission register (not shown in FIGS. 11 and 17) in the uncore ofthe processor 1100 for storing the information of the unknowninstructions 132, the operating environment information, a transmissioninformation flag, and a transmission result flag (not shown in FIG. 17),wherein the default values of the transmission information flag and thetransmission result flag are both the second value. The kernel driver150 stores the information of the unknown instruction 132 and theoperating environment information in the transmission register, andstores the transmission information flag of the first value in thetransmission register. Then, the kernel driver 150 reads thetransmission result flag in the transmission register at regularintervals (for example, every 100 milliseconds) to wait for theconversion result to be received. When the transmission result flag readby the kernel driver 150 is the first value, it means that theconversion program 145 has generated the conversion result, and thekernel driver 150 may read the conversion result from the transmissionregister. In addition, the conversion program 145 running on thededicated processing core 190 is set to check whether the transmissioninformation flag in the transmission register is the first value atregular intervals (for example, every 100 milliseconds) when theconversion program 145 is idle. When the transmission information flagin the transmission register is the first value, the conversion program145 reads the information of the unknown instruction 132 and theoperating environment information from the transmission register, andthen sets the transmission information flag in the transmission registerto the second value. Then, the conversion program 145 performs theconversion processing on the unknown instruction 132 according to themethod described above, and generates a conversion result. Then, theconversion program 145 stores the conversion result in the transmissionregister, and stores the transmission result flag whose value is thefirst value in the transmission register. As mentioned above, since thetransmission result flag is the first value, the kernel driver 150 mayread the conversion result from the transmission register and set thetransmission result flag in the transmission register to the secondvalue. Therefore, a data transmission is completed between the kerneldriver 150 and the conversion program 145. In another embodiment, underthe multi-core processor architecture, it is also necessary to store thenumber of the processing core in the transmission register or allocatededicated storage space for each processing core in the transmissionregister, so that the kernel driver 150 running on each processing corecan transmit data with the conversion program 145.

The doorbell mechanism is described below. Also referring to FIGS. 11and 17, in one embodiment, the designer of the processor 1100 may set atransmission register (not shown in FIGS. 11 and 17) in the uncore ofthe processor 1100 to store the information of the unknown instruction132 and the operating environment information (not shown in FIG. 17).After the kernel driver 150 stores the information of the unknowninstruction 132 and the operating environment information in thetransmission register, the kernel driver 150 notifies the conversionprogram 145 running on the dedicated processor 190 through an interrupt.In response to the interrupt, the conversion program 145 reads theinformation of the unknown instruction 132 and the operating environmentinformation from the transmission register, and generates the conversionresult. Then, the conversion program 145 stores the conversion result inthe transmission register, and informs the kernel driver 150 through aninterrupt. In response to the interrupt, the kernel driver 150 reads theconversion result from the transmission register. Therefore, a datatransmission is completed between the kernel driver 150 and theconversion program 145. As for how to set interrupts, for example,define the interrupt service programs for the kernel driver 150 and theconversion program 145, and define corresponding codes of the interruptvectors, have been described above, so the details related to how to setinterrupts will be omitted. In another embodiment, a hardware interruptsignal line (PIN) may also be added to the processor 1100 and/or thededicated processor 190 separately, and the kernel driver 150 and/or theconversion program 145 may trigger an interrupt through the hardwareinterrupt signal line to complete the data transmission.

Other processing procedures in this embodiment are the same as those inthe third embodiment, so the details related to processing procedureswill be omitted.

In another embodiment, the functions of the conversion program 145described in the first, second, and fourth embodiments may beimplemented in a hardware circuit.

As shown above, similar to the third embodiment, in this embodiment, theconversion of the new instructions is also performed by the kerneldriver 150 of the operating system 120. The difference from the thirdembodiment is that, in this embodiment, the conversion program 145 runson the dedicated processing core 190. In this embodiment, since theconversion program 145 runs on the dedicated processing core 190, theexecution speed is faster. In addition, since there is no need toexecute a conversion program 145 in each processing core, the workloadof other processing cores of the processor is reduced.

FIG. 18 shows a flowchart of executing a new instruction according to anembodiment of the present disclosure. Please refer to FIGS. 11, 17, and18. As described in the third embodiment and this embodiment, theprocessor 1100 receives an instruction (S1805). When the receivedinstruction is an unknown instruction, the processor 1100 executes aconversion program through the operating system 120 (S1810). In theconversion program, the processor 1100 determines whether the receivedinstruction is a new instruction (S1815), and converts the receivedinstruction into at least one old instruction when the receivedinstruction is a new instruction (S1820). Finally, the processor 1100executes the at least one old instruction (S1825). Steps S1805, S1815,S1820, and S1825 in FIG. 18 have been described in detail in the firstembodiment, so the details related to steps S1805, S1815, S1820, andS1825 will be omitted. Step S1810 is described below.

In step S1810, when the received instruction is an unknown instruction,the processor 1100 executes a conversion program through the operatingsystem. Specifically, as shown in the description of the thirdembodiment and this embodiment, when the received instruction is anunknown instruction, the instruction retiring unit 245 generates anunknown instruction exception. In response to the unknown instructionexception, the processor 1100 executes a microcode handler of theunknown instruction exception. In the microcode handler of the unknowninstruction exception, the processor 1100 calls the kernel driver 150 ofthe operating system. The kernel driver 150 of the operating system thencalls the conversion program 145.

FIG. 19 is a flow chart of executing a new instruction according to anembodiment of the present disclosure. Please refer to FIGS. 11, 17, and19. As described in the first, second, third and this embodiment, theprocessor 1100 receives an instruction (S1905). When the receivedinstruction is an unknown instruction, the processor 1100 executes aconversion program (S1910). In the conversion program, the processor1100 determines whether the received instruction is a new instruction(S1915), and converts the received instruction into at least one oldinstruction when the received instruction is a new instruction (S1920).Finally, the processor 1100 simulates the execution of the receivedinstruction by executing the at least one old instruction (S1925). StepsS1905, S1915, S1920, and S1925 in FIG. 19 have been described in detailin the first embodiment, so the details related to steps S1905, S1915,S1920, and S1925 will be omitted. Next, step S1910 is described.

In step S1910, when the received instruction is an unknown instruction,the processor 1100 executes a conversion program. Specifically, asdescribed in the first embodiment, the second embodiment, the thirdembodiment, and the present embodiment, when the received instruction isan unknown instruction, the instruction retiring unit 245 generates anunknown instruction exception. In response to the unknown instructionexception, the processor 1100 executes a microcode handler of theunknown instruction exception.

Specifically, in the first embodiment, the microcode handler of theunknown instruction exception generates a system management interrupt(#SMI). In response to the system management interrupt, the processor1100 enters the system management mode. In the system management mode,the processor 1100 executes the simulator 142, and the simulator 142calls the conversion program 145. In the second embodiment, themicrocode handler of the unknown instruction exception directly callsthe conversion program 145. In the third embodiment and this embodiment,the microcode handler of the unknown instruction exception calls thekernel driver 150 of the operating system 120. Then the kernel driver150 of the operating system 120 calls the conversion program 145.

FIG. 20 is a flowchart showing the conversion of the new instructionaccording to an embodiment of the present disclosure. Please refer toFIGS. 11, 17, and 20. As shown in the description of the first, second,third and this embodiment, the conversion program 145 receives aninstruction, wherein the received instruction is an unknown instruction(S2005), and determines whether the received instruction is a newinstruction (S2010). When the received instruction is a new instruction,the conversion program 145 converts the received instruction into atleast one old instruction (S2015). In the foregoing, steps S2005, S2010,and S2015 of FIG. 20 have been described in detail, so the detailsrelated to steps S2005, S2010, and S2015 will be omitted.

Having described embodiments of the present disclosure, an exemplaryoperating environment in which embodiments of the present disclosure maybe implemented is described below. Referring to FIG. 21, an exemplaryoperating environment for implementing embodiments of the presentdisclosure is shown and generally known as a computing device 2100. Thecomputing device 2100 is merely an example of a suitable computingenvironment and is not intended to limit the scope of use orfunctionality of the disclosure. Neither should the computing device2100 be interpreted as having any dependency or requirement relating toany one or combination of components illustrated.

The disclosure may be realized by means of the computer ormachine-useable instructions, including computer-executable instructionssuch as program modules, being executed by a computer or other machine,such as a personal data assistant (PDA) or other handheld device.Generally, program modules may include routines, programs, objects,components, data structures, etc., and refer to code that performsparticular tasks or implements particular abstract data types. Thedisclosure may be implemented in a variety of system configurations,including handheld devices, consumer electronics, general-purposecomputers, more specialty computing devices, etc. The disclosure mayalso be implemented in distributed computing environments where tasksare performed by remote-processing devices that are linked by acommunication network.

With reference to FIG. 21, the computing device 2100 may include a bus2110 that is directly or indirectly coupled to the following devices:one or more memories 2112, one or more processors 2114, one or moredisplay components 2116, one or more input/output (I/O) ports 2118, oneor more input/output components 2120, and an power supply 2122. The bus2110 may be one or more kinds of busses (such as an address bus, databus, or any combination thereof). Although the various blocks of FIG. 21are shown with lines for the sake of clarity, and in reality, theboundaries of the various components are not specific. For example, thedisplay component such as a display device may be considered an I/Ocomponent and the processor may include a memory.

The computing device 2100 typically includes a variety ofcomputer-readable media. The computer-readable media can be anyavailable media that can be accessed by computing device 2100 andincludes both volatile and nonvolatile media, removable andnon-removable media. By way of example, not limitation,computer-readable media may comprise computer storage media andcommunication media. The computer storage media may include volatile andnonvolatile, removable and non-removable media implemented in any methodor technology for storage of information such as computer-readableinstructions, data structures, program modules or other data. Thecomputer storage media may include, but not limit to, random accessmemory (RAM), read-only memory (ROM), electrically-erasable programmableread-only memory (EEPROM), flash memory or other memory technology,compact disc read-only memory (CD-ROM), digital versatile disks (DVD) orother optical disk storage, magnetic cassettes, magnetic tape, magneticdisk storage or other magnetic storage devices, or any other mediumwhich can be used to store the desired information and which can beaccessed by the computing device 2100. The computer storage media maynot comprise signals per se.

The communication media typically embodies computer-readableinstructions, data structures, program modules or other data in amodulated data signal such as a carrier wave or other transportmechanism and includes any information delivery media. The term“modulated data signal” means a signal that has one or more of itscharacteristics set or changed in such a manner as to encode informationin the signal. By way of example, but not limitation, communicationmedia includes wired media such as a wired network or direct-wiredconnection, and wireless media such as acoustic, RF, infrared and otherwireless media or any combination thereof.

The memory 2112 may include computer-storage media in the form ofvolatile and/or nonvolatile memory. The memory may be removable,non-removable, or a combination thereof. Exemplary hardware devicesinclude solid-state memory, hard drives, optical-disc drives, etc. Thesystem management memory in the first embodiment is located in thememory 2112.

The computing device 2100 includes one or more processors 2114 that readdata from various entities such as the memory 2112 or the I/O components2120. The display component(s) 2116 present data indications to a useror to another device. Exemplary presentation components include adisplay device, speaker, printing component, vibrating component, etc.

The I/O ports 2118 allow the computing device 2100 to be logicallycoupled to other devices including the I/O components 2120, some ofwhich may be embedded. Illustrative components include a microphone,joystick, game pad, satellite dish, scanner, printer, wireless device,etc. The I/O components 2120 may provide a natural user interface (NUI)that processes gestures, voice, or other physiological inputs generatedby a user. For example, inputs may be transmitted to an appropriatenetwork element for further processing. A NUI may be implemented torealize speech recognition, touch and stylus recognition, facialrecognition, biometric recognition, gesture recognition both on screenand adjacent to the screen, air gestures, head and eye tracking, touchrecognition associated with displays on the computing device 2100, orany combination thereof. The computing device 2100 may be equipped withdepth cameras, such as stereoscopic camera systems, infrared camerasystems, RGB camera systems, or any combination thereof, to realizegesture detection and recognition. Furthermore, the computing device2100 may be equipped with accelerometers or gyroscopes that enabledetection of motion. The output of the accelerometers or gyroscopes maybe provided to the display of the computing device 2100 to carry outimmersive augmented reality or virtual reality.

Furthermore, the processor 2114 in the computing device 2100 can executethe program code in the memory 2112 to perform the above-describedactions and steps or other descriptions herein.

It should be understood that any specific order or hierarchy of steps inany disclosed process is an example of a sample approach. Based upondesign preferences, it should be understood that the specific order orhierarchy of steps in the processes may be rearranged while remainingwithin the scope of the present disclosure. The accompanying methodclaims present elements of the various steps in a sample order, and arenot meant to be limited to the specific order or hierarchy presented.

Use of ordinal terms such as “first,” “second,” “third,” etc., in theclaims to modify a claim element does not by itself connote anypriority, precedence, or order of one claim element over another or thetemporal order in which acts of a method are performed, but are usedmerely as labels to distinguish one claim element having a certain namefrom another element having the same name (but for use of the ordinalterm) to distinguish the claim elements.

Through the method for executing new instructions and the system forexecuting new instructions provided by the present disclosure, the newinstructions can be executed on the previous-generation processorwithout modifying the hardware architecture of the processing core.

While the disclosure has been described by way of example and in termsof the preferred embodiments, it should be understood that thedisclosure is not limited to the disclosed embodiments. On the contrary,it is intended to cover various modifications and similar arrangements(as would be apparent to those skilled in the art). Therefore, the scopeof the appended claims should be accorded the broadest interpretation soas to encompass all such modifications and similar arrangements.

What is claimed is:
 1. A method for executing new instructions, used ina processor, comprising: receiving an instruction; generating an unknowninstruction exception when the received instruction is an unknowninstruction; in response to the unknown instruction exception, enteringa system management mode; and in the system management mode, executingthe following steps through a conversion program: determining whetherthe received instruction is a new instruction; and simulating theexecution of the received instruction by executing at least one oldinstruction when the received instruction is a new instruction.
 2. Themethod for executing new instructions as claimed in claim 1, wherein thereceived instruction is an instruction set architecture instruction, andthe at least one old instruction is an instruction set architectureinstruction.
 3. The method for executing new instructions as claimed inclaim 1, further comprising: decoding the at least one old instructioninto at least one microinstruction; and executing the at least onemicroinstruction.
 4. The method for executing new instructions asclaimed in claim 1, further comprising: writing a emulation flag into amicroarchitecture register when the received instruction is an unknowninstruction; and generating a system management interrupt.
 5. The methodfor executing new instructions as claimed in claim 4, wherein theemulation flag is the first value, which is used to indicate that thereceived instruction is an instruction to be simulated.
 6. The methodfor executing new instructions as claimed in claim 1, furthercomprising: obtaining a emulation flag, an instruction pointer of thereceived instruction, the machine code of the received instruction, andthe operating environment information of the received instruction from amicroarchitecture register; storing the emulation flag, the instructionpointer of the received instruction, the machine code, and the operatingenvironment information in a system management memory; and entering thesystem management mode.
 7. The method for executing new instructions asclaimed in claim 6, wherein in the system management mode, the methodfurther comprises: obtaining the emulation flag from the systemmanagement memory; and determining whether the received instruction is anew instruction according to the machine code when the emulation flag isthe first value, wherein the first value indicates that the receivedinstruction is an instruction to be simulated.
 8. The method forexecuting new instructions as claimed in claim 6, wherein in the systemmanagement mode and when the received instruction is a new instruction,the method further comprises: generating a decoding exception when thereceived instruction cannot be executed in the operating environment;and storing the decoding exception is in the system management memory,and set an exception flag in the system management memory.
 9. The methodfor executing new instructions as claimed in claim 6, furthercomprising: writing the emulation flag, the instruction pointer of thereceived instruction, the machine code, and the operating environmentinformation into the microarchitecture register when the receivedinstruction is an unknown instruction.
 10. The method for executing newinstructions as claimed in claim 1, wherein in the system managementmode, the method further comprises: obtaining the machine code of thereceived instruction from a system management memory; decoding themachine code to obtain the operation code of the received instruction;and determining whether the received instruction is a new instructionaccording to the operation code.
 11. The method for executing newinstructions as claimed in claim 10, wherein in the system managementmode and when the received instruction is a new instruction, the methodfurther comprises: generating the at least one old instruction accordingto the operation code; and executing the at least one old instruction.12. The method for executing new instructions as claimed in claim 10,further comprising: decoding the machine code to obtain other decodinginformation of the received instruction, wherein the other decodinginformation comprises a source operand and a destination operand; andexecuting the at least one old instruction according to the otherdecoding information.
 13. The method for executing new instructions asclaimed in claim 10, wherein in the system management mode and when thereceived instruction is not a new instruction, the method furthercomprises: generating an exception code of an unknown instructionexception; and storing the exception code in the system managementmemory, and setting an exception flag in the system management memory.14. The method for executing new instructions as claimed in claim 1,wherein in the system management mode, the method further comprises:reading an instruction pointer of the received instruction from a systemmanagement memory; reading a machine code of the received instructionfrom the system memory according to the instruction pointer; anddetermining whether the received instruction is a new instructionaccording to the machine code.
 15. The method for executing newinstructions as claimed in claim 1, wherein when the receivedinstruction is a new instruction, the method further comprises: in thesystem management mode, storing a simulation execution result in asystem management memory, wherein the simulation execution result isobtained by executing the at least one old instruction.
 16. The methodfor executing new instructions as claimed in claim 15, wherein when thereceived instruction is a new instruction, the method further comprises:writing the simulation execution result stored in the system managementmemory into an architecture register when exiting the system managementmode.
 17. The method for executing new instructions as claimed in claim1, wherein when the received instruction is a new instruction, themethod further comprises: calculating a length of the receivedinstruction; and updating the instruction pointer stored in the systemmanagement memory to: EIP+Length when no exception occurs during theexecution of the at least one old instruction, wherein EIP is theinstruction pointer of the received instruction, and Length is thelength.
 18. The method for executing new instructions as claimed inclaim 1, wherein when the received instruction is a new instruction, themethod further comprises: when an exception occurs during the executionof the at least one old instruction and the exception is a trap, theinstruction pointer stored in the system management memory is updatedto: EIP+Length, wherein EIP is the instruction pointer of the receivedinstruction, and Length is a length of the received instruction.
 19. Themethod for executing new instructions as claimed in claim 1, wherein theconversion program is pre-stored in a basic input output system (BIOS).20. The method for executing new instructions as claimed in claim 19,further comprising: executing the basic input output system; and loadingthe conversion program into a system management memory.
 21. The methodfor executing new instructions as claimed in claim 1, furthercomprising: in the system management mode: obtaining an emulation flagfrom a system management memory; and executing the conversion programwhen the emulation flag is the first value, wherein the first valueindicates that the received instruction is an instruction to besimulated.
 22. The method for executing new instructions as claimed inclaim 1, wherein when the received instruction is a new instruction, themethod further comprises: determining whether an exception occurs duringthe execution of the at least one old instruction; and storing theexception in a system management memory and setting an exception flag inthe system management memory when the exception occurs.
 23. The methodfor executing new instructions as claimed in claim 22, wherein theexception comprises decoding exceptions and runtime exceptions.
 24. Themethod for executing new instructions as claimed in claim 22, whereinwhen the received instruction is a new instruction, the method furthercomprises: determining whether the exception has occurred according tothe exception flag stored in the system management memory; and when thedetermination result is that the exception has occurred, executing themicrocode handler of the exception stored in the system managementmemory after exiting the system management mode.
 25. The method forexecuting new instructions as claimed in claim 22, wherein when thereceived instruction is a new instruction, the method further comprises:when the exception is a trap and exiting the system management mode,using the information stored in the system management memory to restorethe value stored in the architecture register.
 26. The method forexecuting new instructions as claimed in claim 1, wherein when thereceived instruction is a new instruction and the operand of thereceived instruction is a new architecture register, the newarchitecture register is simulated using a system
 27. The method forexecuting new instructions as claimed in claim 26, wherein when the newarchitecture register is a destination operand of the receivedinstruction, the method further comprises: storing the simulationexecution result of the received instruction into the system managementmemory after simulating the execution of the received instruction. 28.The method for executing new instructions as claimed in claim 27,wherein when the new architecture register is a destination operand ofthe received instruction, the method further comprises: not storing thecalculation results stored in the system management memory in thearchitecture register when exiting the system management mode.
 29. Themethod for executing new instructions as claimed in claim 27, furthercomprising: directly using the operation result stored in the a systemmanagement memory to simulate the execution of another receivedinstruction when the another received instruction is a new instructionand the new architecture register is a source operand of the anotherreceived instruction.
 30. The method for executing new instructions asclaimed in claim 1, wherein when the received instruction is a newinstruction, and the received instruction comprises a memory operand,the method further comprises: converting a virtual address of the memoryoperand into a physical address; and reading the value of the memoryoperand according to the physical address, wherein the physical addressis not in the system management memory.
 31. The method for executing newinstructions as claimed in claim 30, wherein when the receivedinstruction is a new instruction, and the received instruction comprisesa memory operand, the method further comprises: converting the virtualaddress of the memory operand into the physical address through aphysical memory direct access interface by accessing a page table. 32.The method for executing new instructions as claimed in claim 30,wherein when the received instruction is a new instruction and thereceived instruction comprises a memory operand, the method furthercomprises: reading a value of the memory operand according to thephysical address through a model specific register.
 33. The method forexecuting new instructions as claimed in claim 32, wherein when thereceived instruction is a new instruction and the received instructioncomprises a memory operand, the method further comprises: writing anaddress of the model specific register into a first register; writingthe physical address into a second register; and executing a write MSR(WRMSR) instruction to store a value of the memory operand in the modelspecific register.
 34. The method for executing new instructions asclaimed in claim 33, wherein when the received instruction is a newinstruction and the received instruction comprises a memory operand, themethod further comprises: executing a read MSR (RDMSR) instruction toread the value of the memory operand from the model specific register,and storing the value of the memory operand in the second register. 35.The method for executing new instructions as claimed in claim 33,wherein when the received instruction is a new instruction and thereceived instruction comprises a memory operand, the method furthercomprises: loading the value of the memory operand from the systemmemory to the model specific register by executing a loadmicroinstruction from the physical address after executing the write MSR(WRMSR) instruction.
 36. A system for executing new instructions,comprising: an instruction decoding unit, receiving an instruction, anddetermining whether the received instruction is an unknown instruction;an instruction retiring unit, generating an unknown instructionexception when the received instruction is an unknown instruction; inresponse to the unknown instruction exception, the system for executingthe new instructions executes the following steps through a conversionprogram: determining whether the received instruction is a newinstruction; and simulating the execution of the received instruction byexecuting at least one old instruction when the received instruction isa new instruction.
 37. The system for executing new instructions asclaimed in claim 36, wherein the received instruction is an instructionset architecture instruction, and the at least one old instruction is aninstruction set architecture instruction.
 38. The system for executingnew instructions as claimed in claim 36, wherein the system forexecuting new instructions decodes the at least one old instruction intoat least one microinstruction, and executes the at least onemicroinstruction.
 39. The system for executing new instructions asclaimed in claim 36, wherein the system for executing new instructionswrites a emulation flag into a microarchitecture register when thereceived instruction is an unknown instruction, and the system forexecuting new instructions generates a system management interrupt. 40.The system for executing new instructions as claimed in claim 39,wherein the emulation flag is the first value, which is used to indicatethat the received instruction is an instruction to be simulated.
 41. Thesystem for executing new instructions as claimed in claim 36, wherein inresponse to a system management interrupt, the system for executing newinstructions obtains a emulation flag, an instruction pointer of thereceived instruction, the machine code of the received instruction, andthe operating environment information of the received instruction from amicroarchitecture register, wherein the emulation flag is a first value,which is used to indicate that the received instruction is aninstruction to be simulated; the system for executing new instructionsstores the emulation flag, the instruction pointer of the receivedinstruction, the machine code, and the operating environment informationin a system management memory, and enters the system management mode.42. The system for executing new instructions as claimed in claim 41,wherein in the system management mode, the system for executing newinstructions obtains the emulation flag from the system managementmemory, and determines whether the received instruction is a newinstruction according to the machine code when the emulation flag is thefirst value, wherein the first value indicates that the receivedinstruction is an instruction to be simulated.
 43. The system forexecuting new instructions as claimed in claim 41, wherein in the systemmanagement mode, when the received instruction is a new instruction andthe received instruction cannot be executed in the operatingenvironment, the system for executing new instructions generates adecoding exception, stores the decoding exception is in the systemmanagement memory, and sets an exception flag in the system managementmemory.
 44. The system for executing new instructions as claimed inclaim 41, wherein when the received instruction is an unknowninstruction, the system for executing new instructions writes theemulation flag, the instruction pointer of the received instruction, themachine code, and the operating environment information into themicroarchitecture register.
 45. The system for executing newinstructions as claimed in claim 36, wherein in the system managementmode, the system for executing new instructions obtains the machine codeof the received instruction from a system management memory, decodes themachine code to obtain the operation code of the received instruction,and determines whether the received instruction is a new instructionaccording to the operation code.
 46. The system for executing newinstructions as claimed in claim 45, wherein in the system managementmode, when the received instruction is a new instruction, the system forexecuting new instructions generates the at least one old instructionaccording to the operation code, and executes the at least one oldinstruction.
 47. The system for executing new instructions as claimed inclaim 45, wherein the system for executing new instructions decodes themachine code to obtain other decoding information of the receivedinstruction, wherein the other decoding information comprises a sourceoperand and a destination operand; and the system for executing newinstruction executes the at least one old instruction according to theother decoding information.
 48. The system for executing newinstructions as claimed in claim 45, wherein in the system managementmode and when the received instruction is not a new instruction, thesystem for executing new instructions generates an exception code of anunknown instruction exception, stores the exception code in the systemmanagement memory, and sets an exception flag in the system managementmemory.
 49. The system for executing new instructions as claimed inclaim 36, wherein in the system management mode, the system forexecuting new instructions reads an instruction pointer of the receivedinstruction from a system management memory, reads a machine code of thereceived instruction from the system memory according to the instructionpointer, and determines whether the received instruction is a newinstruction according to the machine code.
 50. The system for executingnew instructions as claimed in claim 36, wherein when the receivedinstruction is a new instruction, in the system management mode, thesystem for executing new instructions stores a simulation executionresult in a system management memory, wherein the simulation executionresult is obtained by executing the at least one old instruction. 51.The system for executing new instructions as claimed in claim 50,wherein when the received instruction is a new instruction and thesystem for executing new instructions exits the system management mode,the system for executing new instructions writes the simulationexecution result stored in the system management memory into anarchitecture register.
 52. The system for executing new instructions asclaimed in claim 36, wherein when the received instruction is a newinstruction, the system for executing new instructions calculates alength of the received instruction; and the system for executing newinstructions updates the instruction pointer stored in the systemmanagement memory to: EIP+Length when no exception occurs during theexecution of the at least one old instruction, wherein EIP is theinstruction pointer of the received instruction, and Length is thelength.
 53. The system for executing new instructions as claimed inclaim 36, wherein when the received instruction is a new instruction,and when an exception occurs during the execution of the at least oneold instruction and the exception is a trap, the system for executingnew instructions updates the instruction pointer stored in the systemmanagement memory to: EIP+Length, wherein EIP is the instruction pointerof the received instruction, and Length is a length of the receivedinstruction.
 54. The system for executing new instructions as claimed inclaim 36, wherein the conversion program is pre-stored in a basic inputoutput system (BIOS).
 55. The system for executing new instructions asclaimed in claim 54, wherein the system for executing new instructionsexecutes the basic input output system and loads the conversion programinto a system management memory.
 56. The system for executing newinstructions as claimed in claim 36, wherein in the system managementmode, the system for executing new instructions obtains an emulationflag from a system management memory and executes the conversion programwhen the emulation flag is the first value, wherein the first valueindicates that the received instruction is an instruction to besimulated.
 57. The system for executing new instructions as claimed inclaim 36, wherein when the received instruction is a new instruction,the system for executing new instructions determines whether anexception occurs during the execution of the at least one oldinstruction, stores the exception in a system management memory and setsan exception flag in the system management memory when the exceptionoccurs.
 58. The system for executing new instructions as claimed inclaim 57, wherein the exception comprises decoding exceptions andruntime exceptions.
 59. The system for executing new instructions asclaimed in claim 57, wherein when the received instruction is a newinstruction, the system for executing new stored in the systemmanagement memory; when the determination result is that the exceptionhas occurred, the system for executing new instructions executes themicrocode handler of the exception stored in the system managementmemory after exiting the system management mode.
 60. The system forexecuting new instructions as claimed in claim 57, wherein when thereceived instruction is a new instruction, the exception is a trap andthe system for executing new instructions exits the system managementmode, the system for executing new instructions uses the informationstored in the system management memory to restore the value stored inthe architecture register.
 61. The system for executing new instructionsas claimed in claim 36, wherein when the received instruction is a newinstruction and the operand of the received instruction is a newarchitecture register, the new architecture register is simulated usinga system management memory in the system management mode.
 62. The systemfor executing new instructions as claimed in claim 61, wherein when thenew architecture register is a destination operand of the receivedinstruction, the system for executing new instructions stores thesimulation execution result of the received instruction into the systemmanagement memory after simulating the execution of the receivedinstruction.
 63. The system for executing new instructions as claimed inclaim 62, wherein when the new architecture register is a destinationoperand of the received instruction and the system for executing newinstructions exits the system management mode, the system for executingnew instructions does not store the calculation results stored in thesystem management memory in the architecture register.
 64. The systemfor executing new instructions as claimed in claim 62, wherein whenanother received instruction is a new instruction and the newarchitecture register is a source operand of the another receivedinstruction, the system for executing new instructions directly uses theoperation result stored in the a system management memory to simulatethe execution of the another received instruction.
 65. The system forexecuting new instructions as claimed in claim 36, wherein when thereceived instruction is a new instruction, and the received instructioncomprises a memory operand, the system for executing new instructionsconverts a virtual address of the memory operand into a physicaladdress, and reads the value of the memory operand according to thephysical address, wherein the physical address is not in the systemmanagement memory.
 66. The system for executing new instructions asclaimed in claim 65, wherein when the received instruction is a newinstruction, and the received instruction comprises a memory operand,the system for executing new instructions converts the virtual addressof the memory operand into a physical address through a physical memorydirect access interface by accessing a page table.
 67. The system forexecuting new instructions as claimed in claim 65, wherein when thereceived instruction is a new instruction and the received instructioncomprises a memory operand, the system for executing new instructionsreads a value of the memory operand according to the physical addressthrough a model specific register.
 68. The system for executing newinstructions as claimed in claim 67, wherein when the receivedinstruction is a new instruction and the received instruction comprisesa memory operand, the system for executing new instructions writes anaddress of the model specific register into a first register, writes thephysical address into a second register, and executes a write MSR(WRMSR) instruction to store a value of the memory operand in the modelspecific register.
 69. The system for executing new instructions asclaimed in claim 68, wherein when the received instruction is a newinstruction and the received instruction comprises a memory operand, thesystem for executing new instructions executes a read MSR (RDMSR)instruction to read the value of the memory operand from the modelspecific register, and stores the value of the memory operand in thesecond register.
 70. The system for executing new instructions asclaimed in claim 68, wherein when the received instruction is a newinstruction and the received instruction comprises a memory operand, thesystem for executing new instructions loads the value of the memoryoperand from the system memory to the model specific register byexecuting a load microinstruction from the physical address afterexecuting the write MSR (WRMSR) instruction.